公开(公告)号：US06937496B2

公开(公告)日：2005-08-30

申请号：US10757441

申请日：2004-01-15

Applicant: Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

Inventor： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

IPC: G11C11/413 ,  G05F1/56 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G11C11/36

CPC classification number: G11C5/14 ,  G11C5/147

Abstract: A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

Abstract translation: 一种半导体器件，具有提供有第一工作电压的第一电路块，提供有第二工作电压的第二电路块，用于响应于第一工作电压产生第三工作电压的电压产生电路，以及提供的第三电路块 具有第三工作电压。 优选地，产生第三工作电压，使得通过升压转换器将第一工作电压增加到第四工作电压，然后通过电压下变频器将第四工作电压降至第三工作电压。 因此，即使在电源电压下降的情况下，即使使用相对波动的电压也能够内部稳定工作的电源。

公开(公告)号：US06906575B2

公开(公告)日：2005-06-14

申请号：US10644777

申请日：2003-08-21

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G11C5/14 ,  G11C11/4074 ,  H02M3/07 ,  H03K19/0175 ,  G05F3/02

CPC classification number: G11C11/4074 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/077

Abstract: A semiconductor integrated circuit device having an internal voltage generating circuit which generates a voltage two or more times higher than an operating voltage while at the same time reducing the voltage applied to a device, thereby ensuring the device reliability. In a charge pump circuit driven by supply voltage VDD, a maximum of 2 VDD or a similar level voltage is applied between the drain and source of a MOSFET, the MOSFET being connected in series with a conduction MOSFET of the same type, the gate of which is supplied with VD−VDD, or a potential which is VDD lower than VD, the drain potential before its connection. The gate potential is obtained directly from a node in said charge pump which generates a voltage pulse synchronized with the voltage between the drain and source of that MOSFET, or through another rectifier device branched via a capacitor from the node.

Abstract translation: 一种具有内部电压产生电路的半导体集成电路器件，其产生比工作电压高两倍或更多倍的电压，同时降低施加到器件的电压，从而确保器件的可靠性。 在由电源电压VDD驱动的电荷泵电路中，在MOSFET的漏极和源极之间施加最大值为2 VDD或类似的电平电压，MOSFET与相同类型的导通MOSFET串联连接，栅极 其提供有VD-VDD或VDD低于VD的电位，其连接之前的漏极电位。 栅极电位直接从所述电荷泵中的节点获得，其产生与该MOSFET的漏极和源极之间的电压同步的电压脉冲，或通过经由电容器从该节点分支的另一个整流器件。

公开(公告)号：US06905995B2

公开(公告)日：2005-06-14

申请号：US10390717

申请日：2003-03-19

Applicant: Takashi Kamiya ,  Osamu Otani ,  Kaname Ueda ,  Syunichi Yuri ,  Hitoshi Tanaka

Inventor： Takashi Kamiya ,  Osamu Otani ,  Kaname Ueda ,  Syunichi Yuri ,  Hitoshi Tanaka

IPC: C04B35/628 ,  C04B35/46 ,  H01B3/12 ,  H01G4/12 ,  C04B35/465 ,  B32B18/00

CPC classification number: C04B35/62892 ,  B32B18/00 ,  B82Y30/00 ,  C04B35/468 ,  C04B35/4682 ,  C04B35/62807 ,  C04B35/6281 ,  C04B35/62815 ,  C04B35/62818 ,  C04B35/62886 ,  C04B2235/3203 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3232 ,  C04B2235/3236 ,  C04B2235/3239 ,  C04B2235/3241 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3262 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/441 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2237/704 ,  H01G4/1209 ,  Y10T428/2991 ,  Y10T428/2993

Abstract: A ceramic powder including ceramic main component particles and additive component particles deposited on the surfaces of the main component particles. The mean particle size of the main component particles is made not more than 1.5 μm, and the mean particle size of the additive component particles is made not more than 0.31 μm. The content of the additive composition particles is made 0.1 to 5 wt % with respect to 100 parts by weight of the ceramic powder. The dispersibility of the additive component particles with respect to the main component particles is improved and the uniformity of the structure is promoted to suppress the occurrence of hetero phases. A multilayer ceramic electronic device having a high insulation breakdown voltage and long life even with a thickness of the dielectric layers of not more than 3 μm are provided.

Abstract translation: 一种陶瓷粉末，其包括沉积在主要组分颗粒表面上的陶瓷主要成分颗粒和添加剂组分颗粒。 主成分粒子的平均粒径为1.5μm以下，添加成分粒子的平均粒径为0.31μm以下。 添加剂组合物颗粒的含量相对于100重量份的陶瓷粉末为0.1〜5重量％。 添加成分粒子相对于主成分粒子的分散性提高，结构的均匀性得到提高，抑制杂相的发生。 提供具有高绝缘击穿电压和长寿命的多层陶瓷电子器件，即使电介质层的厚度不大于3μm。

公开(公告)号：US06711071B2

公开(公告)日：2004-03-23

申请号：US10319511

申请日：2002-12-16

Applicant: Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

Inventor： Hiroyuki Mizuno ,  Takao Watanabe ,  Mitsuru Hiraki ,  Hitoshi Tanaka

IPC: G11C700

CPC classification number: G11C5/14 ,  G11C5/147

Abstract: A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.

Abstract translation: 一种半导体器件，具有提供有第一工作电压的第一电路块，提供有第二工作电压的第二电路块，用于响应于第一工作电压产生第三工作电压的电压产生电路，以及提供的第三电路块 具有第三工作电压。 优选地，产生第三工作电压，使得通过升压转换器将第一工作电压增加到第四工作电压，然后通过电压下变频器将第四工作电压降至第三工作电压。 因此，即使在电源电压下降的情况下，即使使用相对波动的电压也能够内部稳定地工作的电源。

公开(公告)号：US06414530B2

公开(公告)日：2002-07-02

申请号：US09832019

申请日：2001-04-11

Applicant: Hiromasa Noda ,  Masakazu Aoki ,  Hitoshi Tanaka ,  Hideyuki Aoki

Inventor： Hiromasa Noda ,  Masakazu Aoki ,  Hitoshi Tanaka ,  Hideyuki Aoki

IPC: H03K1126

CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1504

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract translation: 格子状延迟电路被配置为其中分别设置有用于分别耦合输入到第一和第二输入端子的两个输入信号的阻抗元件的多个逻辑门电路，并且分别形成通过将输入到第一和第二输入端的输入信号反相而获得的输出信号 和第二信号被使用以在第一信号传送方向和第二信号传送方向上以格子形式布置。 输入时钟信号在第一信号传送方向上被连续地延迟，然后输入到从第一信号传输方向看到的从第一到最后的逻辑门电路。 输出信号从放置在至少多个级的逻辑门电路的输出端获得，如第二信号传送方向所示，并且被布置在第一信号传送方向。

公开(公告)号：US06399971B1

公开(公告)日：2002-06-04

申请号：US09191543

申请日：1998-11-13

Applicant: Hisao Shigematsu ,  Kenji Imanishi ,  Hitoshi Tanaka

Inventor： Hisao Shigematsu ,  Kenji Imanishi ,  Hitoshi Tanaka

IPC: H01L29737

CPC classification number: H01L29/66318 ,  H01L29/1004 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42304 ,  H01L29/7371 ,  H01L31/03046

Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.

Abstract translation: 半导体器件包括集电极层14; 具有连接到集电极层14的一个表面的掺碳GaxIn1-xAsySb1-y层的基极层16; 连接在基底层16的另一个表面上的发射极层18; 与基底层16电连接的碳掺杂GaAsSb层的基极接触层30; 以及形成在基极接触层30上的基极32.这种结构的半导体器件可以具有大大降低的基极电阻RB，由此基于InP / InGaAs的HBT的基于InP / GaInAsSb的HBT可以具有更高的最大振荡频率fmax。 由于碳掺杂半导体层，半导体器件可以具有更高的可靠性。

公开(公告)号：US06182082B2

公开(公告)日：2001-01-30

申请号：US08505631

申请日：1995-07-21

Applicant: Hitoshi Tanaka ,  Satoshi Wakayama ,  Takeo Maruyama ,  Yoichi Yamamoto ,  Hideo Munetika

Inventor： Hitoshi Tanaka ,  Satoshi Wakayama ,  Takeo Maruyama ,  Yoichi Yamamoto ,  Hideo Munetika

IPC: G06F1730

CPC classification number: G06F17/30607 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99944

Abstract: A system for managing an object-oriented database in response to a request issued from an application program includes a database for storing therein both of a class having a definition of an object and an object generated from the class; a generating unit for generating a class and a plurality of attributes based on class definition information and attribute definition information, which are designated by the application program; another generating unit for generating an object to store an attribute value corresponding to the class definition information in accordance with the class definition information, the object generating unit including a-storage control unit for storing the attribute value related to a normal attribute into one storage unit area of the database when the request issued from the application program is related to the normal attribute, and for storing the attribute value related to a clustering attribute into another storage unit area of the database when the request issued from the application program is related to a clustering attribute; and acquiring unit for acquiring information corresponding to an identifier of an attribute required by the application program from any one of the one storage unit area and the another storage unit area, and for storing the acquired information into a memory area.

Abstract translation: 用于响应于从应用程序发出的请求来管理面向对象的数据库的系统包括用于在其中存储具有对象的定义和从类生成的对象的类的数据库; 用于基于由所述应用程序指定的类定义信息和属性定义信息来生成类和多个属性的生成单元; 另一个生成单元，用于根据类定义信息生成存储与类定义信息对应的属性值的对象，对象生成单元包括存储控制单元，用于将与正常属性相关的属性值存储到一个存储单元中 当从应用程序发出的请求与正常属性相关联时，数据库的区域与用于从应用程序发出的请求与应用程序相关的将聚类属性相关的属性值存储到数据库的另一个存储单元区域中 聚类属性; 以及获取单元，用于从一个存储单元区域和另一个存储单元区域中的任一个获取与应用程序所需的属性的标识符相对应的信息，并将获取的信息存储到存储区域中。

公开(公告)号：US6121803A

公开(公告)日：2000-09-19

申请号：US255738

申请日：1999-02-23

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G06F1/26 ,  G06F1/04 ,  G06F1/24 ,  H03K3/355 ,  H03K17/22

CPC classification number: H03K17/223

Abstract: The pulse generator of the present invention comprises a p-channel type MOS transistor 5, n-channel type MOS transistors 6 and 7, and a switch circuit 8. The transistor 5 has a gate electrode coupled to a terminal n11. A voltage level of the terminal n11 is risen according to the time constant witch is decided a resistance value of a resistive element 1 and a capacitance value of a capacitive element 2, when rising a source voltage. These transistors 6 and 7 are constructed in cascade connection. The switch circuit 8 is able selective to short-circuit between one electrode and the other electrode of the transistor 7.

Abstract translation: 本发明的脉冲发生器包括p沟道型MOS晶体管5，n沟道型MOS晶体管6和7以及开关电路8.晶体管5具有耦合到端子n11的栅电极。 当上升源电压时，端子n11的电压根据时间常数上升，决定电阻元件1的电阻值和电容元件2的电容值。 这些晶体管6和7被级联连接。 开关电路8能够选择性地在一个电极和晶体管7的另一个电极之间短路。

公开(公告)号：US6097663A

公开(公告)日：2000-08-01

申请号：US413641

申请日：1999-10-06

Applicant: Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

Inventor： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC: G06F17/50 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/12 ,  H01L27/108 ,  G11C8/00

CPC classification number: G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US6072640A

公开(公告)日：2000-06-06

申请号：US238580

申请日：1999-01-28

Applicant: Hitoshi Tanaka

Inventor： Hitoshi Tanaka

IPC: G02B7/02 ,  G02B7/04 ,  G03B17/08 ,  G02B15/14

CPC classification number: G02B7/021 ,  G02B7/04

Abstract: A waterproof lens barrel which includes at least one water-tight movable barrel which is movable along an optical axis, the water-tight movable barrel includes: an outer barrel that is in sliding contact with an annular sealing member; an inner barrel that is positioned inside said outer barrel; at least one through-hole formed on the outer barrel; and at least one stopper pin that is supported by the inner barrel, the stopper pin being snugly fitted in the through-hole so that no force in the radial direction is inflicted on the outer barrel by the stopper pin, and the relative movement of the inner and outer barrels in the direction of the optical axis is determined by the stopper pin and the through-hole.

Abstract translation: 一种防水透镜筒，包括至少一个沿着光轴可移动的水密可移动的筒体，所述防水活动筒体包括：外筒，其与环形密封件滑动接触; 位于所述外筒内部的内筒; 在外筒上形成的至少一个通孔; 以及由所述内筒支撑的至少一个止动销，所述止动销紧贴地配合在所述通孔中，使得所述止动销不会在所述外筒上施加径向的力，并且所述止动销的相对运动 内，外筒沿光轴方向由止动销和贯通孔决定。