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114 条记录 (耗时 0.031 秒)

    Nonvolatile semiconductor memory device with scalable two transistor memory cells
    72.
    发明授权
    Nonvolatile semiconductor memory device with scalable two transistor memory cells 有权
    具有可伸缩双晶体管存储单元的非易失性半导体存储器件

    公开(公告)号：US07113425B2

    公开(公告)日：2006-09-26

    申请号：US10976626

    申请日：2004-10-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C11/404

    摘要： A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the selected data line. Operation speed is increased, while improving device cell array structure.

    摘要翻译： 非易失性存储器件包括位线，一对数据线和多个可伸缩双晶体管存储器（STTM）单元。 存储单元布置在一对数据之间，以便共享位线。 存储器件还包括数据线选择电路和读出放大电路。 数据线选择电路选择一对数据线之一，并且感测放大电路感测并放大位线与所选数据线之间的电压差。 操作速度提高，同时提高器件单元阵列结构。

    Magnetic memory device and method of fabricating the same
    74.
    发明授权
    Magnetic memory device and method of fabricating the same 失效
    磁记忆装置及其制造方法

    公开(公告)号：US08043869B2

    公开(公告)日：2011-10-25

    申请号：US12915335

    申请日：2010-10-29

    申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

    发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

    IPC分类号： H01L29/82

    CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

    摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

    Single transistor memory device having source and drain insulating regions and method of fabricating the same
    75.
    发明授权
    Single transistor memory device having source and drain insulating regions and method of fabricating the same 有权
    具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法

    公开(公告)号：US07851859B2

    公开(公告)日：2010-12-14

    申请号：US11829113

    申请日：2007-07-27

    申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    IPC分类号： H01L23/62

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

    摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

    摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

    Phase change memory device generating program current and method thereof
    79.
    发明申请
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US20100110781A1

    公开(公告)日：2010-05-06

    申请号：US12654338

    申请日：2009-12-17

    申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C17/16

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    Bias voltage generator and method generating bias voltage for semiconductor memory device
    80.
    发明授权
    Bias voltage generator and method generating bias voltage for semiconductor memory device 有权
    用于半导体存储器件的偏置电压发生器和产生偏置电压的方法

    公开(公告)号：US07548467B2

    公开(公告)日：2009-06-16

    申请号：US11955562

    申请日：2007-12-13

    申请人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    发明人： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC分类号： G11C5/14

    CPC分类号： G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

    摘要： There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

    摘要翻译： 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。