公开(公告)号：US10929749B2

公开(公告)日：2021-02-23

申请号：US15494948

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Narayan Srinivasa ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Ben Ashbaugh ,  Prasoonkumar Surti ,  Feng Chen ,  Barath Lakshmanan ,  Elmoustapha Ould-Ahmed-Vall ,  Liwei Ma ,  Linda L. Hurd ,  Abhishek R. Appu ,  John C. Weast ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Dukhwan Kim ,  Altug Koker ,  Nadathur Rajagopalan Satish

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/28 ,  G06F9/302 ,  G06F15/00 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

公开(公告)号：US20210050070A1

公开(公告)日：2021-02-18

申请号：US17006192

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Travis T. Schluessler ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Jonathan Kennedy

IPC: G11C29/44 ,  G11C29/52 ,  G11C29/00

Abstract: Systems, apparatuses and methods may provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, one or more memory cells in the redundant portion may be substituted for the one or more failed memory cells.

公开(公告)号：US10915608B2

公开(公告)日：2021-02-09

申请号：US16126060

申请日：2018-09-10

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Vidhya Krishnan ,  Sandeep Sodhi ,  Sreekanth Mavila ,  Altug Koker ,  Aditya Navale ,  Scott Janus ,  Changliang Wang

IPC: H04L9/00 ,  G06F21/12 ,  G06T15/00 ,  H04N21/254 ,  G06F9/48 ,  H04L9/08 ,  G06F21/60 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatus and method for scalable content protection. For example, one embodiment of an apparatus comprises: cryptographic management circuitry to securely store one or more keys associated with one or more media apps/applications; a plurality of processing engines, each processing engine comprising circuitry to process media content of the one or more media apps/applications; and a scheduler to schedule processing of the media content by the processing engines; wherein the cryptographic management circuitry is to restore a first cryptographic state including a first key associated with a first media app/application and/or first media content responsive to a request to process the first media content on a first processing engine.

公开(公告)号：US20210035259A1

公开(公告)日：2021-02-04

申请号：US16930935

申请日：2020-07-16

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Saikat Mandal ,  Karol A. Szerszen ,  Saurabh Sharma ,  Vamsee Vardhan Chivukula ,  Abhishek R. Appu ,  Joydeep Ray ,  Prasoonkumar Surti ,  Altug Koker

IPC: G06T1/60 ,  G06F12/0875 ,  G06T1/20

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

公开(公告)号：US20210034135A1

公开(公告)日：2021-02-04

申请号：US16992701

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Mohammed Tameem ,  Altug Koker ,  Kiran C. Veernapu ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Travis T. Schluessler ,  Jonathan Kennedy

IPC: G06F1/3234 ,  G06F13/16 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3287

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.

公开(公告)号：US10909653B2

公开(公告)日：2021-02-02

申请号：US16515794

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Stanley J. Baran ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai R. Chan ,  Jill M. Boyce ,  Fangwen Fu ,  Satya N. Yedidi ,  Sumit Mohan ,  James M. Holland ,  Keith W. Rowe ,  Altug Koker

IPC: G06T1/20 ,  H04N19/156 ,  G06T1/60 ,  G09G5/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3212

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：US10909037B2

公开(公告)日：2021-02-02

申请号：US15493404

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Altug Koker ,  James A. Valerio ,  Prasoonkumar Surti

IPC: G09G5/36 ,  G06F12/0844 ,  G06T1/60

Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.

公开(公告)号：US10908939B2

公开(公告)日：2021-02-02

申请号：US15420376

申请日：2017-01-31

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Altug Koker ,  David Puffer ,  Murali Ramadoss ,  Bryan R. White ,  Hema C. Nalluri ,  Aditya Navale

IPC: G06F9/455 ,  G06T15/00 ,  G06F9/50

Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engine to execute a work element using the data identifying a virtual machine or application associated with the work element, wherein different graphics engines are configured to simultaneously execute workloads belonging to different virtual machines or applications.

公开(公告)号：US10908905B2

公开(公告)日：2021-02-02

申请号：US16599239

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50 ,  G09G5/36 ,  G06F12/0842

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US10902546B2

公开(公告)日：2021-01-26

申请号：US15493324

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Abhishek R. Appu ,  Prasoonkumar Surti ,  Arijit Mukhopadhyay ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/20 ,  H04N9/804 ,  H04N9/808

Abstract: A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.