中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

86 records (took 0.023 seconds)

    BACK SIDE PROCESSING OF INTEGRATED CIRCUIT STRUCTURES TO FORM INSULATION STRUCTURE BETWEEN ADJACENT TRANSISTOR STRUCTURES
    71.
    发明申请
    BACK SIDE PROCESSING OF INTEGRATED CIRCUIT STRUCTURES TO FORM INSULATION STRUCTURE BETWEEN ADJACENT TRANSISTOR STRUCTURES 有权

    公开(公告)号：US20230132053A1

    公开(公告)日：2023-04-27

    申请号：US18087129

    申请日：2022-12-22

    Applicant: Intel Corporation

    Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Patrick MORROW

    IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/12

    Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

    INTEGRATED CIRCUIT STRUCTURES HAVING METAL-CONTAINING SOURCE OR DRAIN STRUCTURES
    72.
    发明申请
    INTEGRATED CIRCUIT STRUCTURES HAVING METAL-CONTAINING SOURCE OR DRAIN STRUCTURES 有权

    公开(公告)号：US20230095007A1

    公开(公告)日：2023-03-30

    申请号：US17485173

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Aaron D. LILAK ,  Cory WEBER ,  Patrick KEYS ,  Navid PAYDAVOSI

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: Integrated circuit structures having metal-containing source or drain structures, and methods of fabricating integrated circuit structures having metal-containing source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include a metal species diffused therein, the metal species further diffused partially into the vertical arrangement of horizontal nanowires.

    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
    73.
    发明申请
    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES 有权

    公开(公告)号：US20220246759A1

    公开(公告)日：2022-08-04

    申请号：US17722142

    申请日：2022-04-15

    Applicant: Intel Corporation

    Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Biswajeet GUHA ,  Tahir GHANI ,  William HSU

    IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

    FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYER AND HAVING A GATE STRESSOR LAYER
    77.
    发明申请
    FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYER AND HAVING A GATE STRESSOR LAYER 有权

    公开(公告)号：US20210408282A1

    公开(公告)日：2021-12-30

    申请号：US16912103

    申请日：2020-06-25

    Applicant: Intel Corporation

    Inventor： Vishal TIWARI ,  Rishabh MEHANDRU ,  Dan S. LAVRIC ,  Michal MLECZKO ,  Szuya S. LIAO

    IPC: H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51

    Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

    FORKSHEET TRANSISTOR ARCHITECTURES
    79.
    发明申请
    FORKSHEET TRANSISTOR ARCHITECTURES 有权

    公开(公告)号：US20210296315A1

    公开(公告)日：2021-09-23

    申请号：US16827566

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Aaron D. LILAK ,  Rishabh MEHANDRU ,  Ehren MANNEBACH ,  Patrick MORROW ,  Willy RACHMADY

    IPC: H01L27/092 ,  H01L29/10 ,  H01L23/498 ,  H01L23/528

    Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.

Patent Agency Ranking