公开(公告)号：US11227859B2

公开(公告)日：2022-01-18

申请号：US16651331

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/367 ,  H01L25/00

Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

公开(公告)号：US20210366862A1

公开(公告)日：2021-11-25

申请号：US17392598

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US11075166B2

公开(公告)日：2021-07-27

申请号：US17005002

申请日：2020-08-27

Applicant: Intel Corporation

Inventor： Eric J. Li ,  Timothy A. Gosselin ,  Yoshihiro Tomita ,  Shawna M. Liff ,  Amram Eitan ,  Mark Saltas

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

公开(公告)号：US11004824B2

公开(公告)日：2021-05-11

申请号：US15389100

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Javier Soto Gonzalez ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US10969574B2

公开(公告)日：2021-04-06

申请号：US16072157

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Thomas L. Sounart ,  Baris Bicen ,  Valluri R. Rao

IPC: G02B26/00 ,  G02B26/08 ,  H01L41/047 ,  H01L41/27 ,  H01L41/314 ,  H01L41/332

Abstract: Embodiments of the invention include a piezo-electric mirror in an microelectronic package and methods of forming the package. According to an embodiment the microelectronic package may include an organic substrate with a cavity formed in the organic substrate. In some embodiments, an actuator is anchored to the organic substrate and extends over the cavity. For example, the actuator may include a first electrode and a piezo-electric layer formed on the first electrode. A second electrode may be formed on the piezo-electric layer. Additionally, a mirror may be formed on the actuator. Embodiments allow for the piezo-electric layer to be formed on an organic package substrate by using low temperature crystallization processes. For example, the piezo-electric layer may be deposited in an amorphous state. Thereafter, a laser annealing process that includes a pulsed laser may be used to crystallize the piezo-electric layer.

公开(公告)号：US20200303611A1

公开(公告)日：2020-09-24

申请号：US16946166

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Thomas L. Sounart ,  Khaled Ahmed ,  Anup Pancholi ,  Shawna M. Liff

IPC: H01L33/62 ,  H01L33/00 ,  H01L25/075

Abstract: A micro-light emitting diode (LED) display and a method of fabricating the same. The method includes aligning a display backplane and a source semiconductor wafer with one another. A plurality of backplane contact pads of a first width are fixed to the backplane and include first solder pads thereon with a second width smaller than the first width. The wafer includes thereon a plurality of micro-LEDs, and a plurality of micro-LED contact pads fixed to the micro-LEDs and having a third width smaller than the first width. The method includes: aligning such that at least some of the micro-LED contact pads register with corresponding first solder pads; releasing at least some of the micro-LEDs from the wafer onto corresponding first solder pads; and forming a plurality of second solder pads by melting the corresponding first solder pads. The second solder pads bond the at least some of the micro-LEDs to corresponding ones of the plurality of backplane contact pads, the second solder pads further extending on said corresponding ones of the plurality of backplane contact pads beyond a footprint thereon of said some of the micro-LEDs.

公开(公告)号：US20200286745A1

公开(公告)日：2020-09-10

申请号：US16648645

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L21/48 ,  H05K3/30 ,  H01L23/538 ,  H01L29/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.

公开(公告)号：US20200279813A1

公开(公告)日：2020-09-03

申请号：US16649950

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US10707171B2

公开(公告)日：2020-07-07

申请号：US15776773

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Tomita Yoshihiro ,  Eric J. Li ,  Shawna M. Liff ,  Javier A. Falcon ,  Joshua D. Heppner

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/04 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/16 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

公开(公告)号：US20200098724A1

公开(公告)日：2020-03-26

申请号：US16142509

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Gerald S. Pasdast

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/36 ,  H01L25/00

Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.