公开(公告)号：US20160293638A1

公开(公告)日：2016-10-06

申请号：US15177715

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Bruce Doris ,  Gauri Karve ,  Qing Liu

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L21/8258 ,  H01L21/84 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US20160293494A1

公开(公告)日：2016-10-06

申请号：US15180158

申请日：2016-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L21/823807 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78684

Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.

公开(公告)号：US09431514B2

公开(公告)日：2016-08-30

申请号：US14577316

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Bruce Doris ,  Gauri Karve

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract translation: 形成硅 - 锗材料的翅片并用外延生长的硅材料层覆盖。 然后形成虚拟晶体管栅极以在鳍的沟道上延伸。 侧壁间隔物形成在虚拟晶体管栅极的两侧，并直接在外延硅层的顶部。 外延生长的源极和漏极区域形成在邻近侧壁间隔物的虚拟晶体管栅极的每一侧上。 虚拟晶体管栅极和外延硅层的一部分（在所述虚设晶体管栅极之下）被去除并由金属栅极代替。

公开(公告)号：US09391200B2

公开(公告)日：2016-07-12

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。

公开(公告)号：US20160181395A1

公开(公告)日：2016-06-23

申请号：US14577316

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Bruce Doris ,  Gauri Karve

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

公开(公告)号：US09306001B1

公开(公告)日：2016-04-05

申请号：US14685745

申请日：2015-04-14

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

Abstract translation: 实施例涉及一种形成鳍式场效应晶体管（FinFET）的漏电流阻挡器的方法。 该方法包括在有源区中形成至少一个具有有源区，非有源区和沟道区的鳍。 该方法还包括暴露非有源区的表面，其中暴露的表面导致基本上在沟道区下面的非有源区的一部分。 该方法还包括通过非有源区的暴露表面注入掺杂剂以形成泄漏电流停止区。

公开(公告)号：US20150372140A1

公开(公告)日：2015-12-24

申请号：US14308045

申请日：2014-06-18

Applicant: STMicroelectronics, Inc ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/30625 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract translation: 描述了用于控制finFET鳍片的回蚀的技术和结构。 一个或多个层可以沉积在翅片上并被蚀刻。 可以使用平坦化层的蚀刻来确定邻近鳍片的一个或多个层的自限制蚀刻高度以及翅片的自限制蚀刻高度。 应变诱发材料可以形成在蚀刻翅片的区域，以引起finFET通道中的应变。

公开(公告)号：US20150279861A1

公开(公告)日：2015-10-01

申请号：US14739736

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A I'Energie atomique et aux Energies alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

Abstract translation: 通过顶部半导体层和绝缘体上半导体（SOI）衬底的掩埋绝缘体层形成沟槽。 执行选择性外延以形成填充沟槽并与处理衬底的半导体材料外延对准的体半导体部分。 在顶部半导体层和体半导体部分上沉积至少一个电介质层，并且被图案化以在顶部半导体层和体半导体部分的选定区域上形成开口。 半导体合金材料直接在顶部半导体层和体半导体部分的物理暴露表面上沉积在开口内。 半导体合金材料在随后的退火中与下面的半导体材料混合。 在SOI区域和体区域的每一个内，根据半导体材料是否与半导体合金材料混合形成两种类型的半导体材料部分。

公开(公告)号：US09105691B2

公开(公告)日：2015-08-11

申请号：US13859013

申请日：2013-04-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick C. Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/00 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76237 ,  H01L21/76897 ,  H01L21/84

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract translation: 一种形成绝缘体上半导体（SOI）器件的方法包括：在SOI衬底中限定浅沟槽隔离（STI）结构，所述SOI衬底包括体层，主体层上的埋层绝缘体（BOX）层，以及 BOX层上的SOI层; 在对应于STI结构的较低位置的本体层的一部分中形成掺杂区域，所述掺杂区域横向延伸到BOX层下面的体层中; 相对于本体层的未掺杂区域选择性地蚀刻本体层的掺杂区域，使得STI结构的较低位置切割BOX层; 并用绝缘体填充材料填充STI结构。

公开(公告)号：US08969966B2

公开(公告)日：2015-03-03

申请号：US13866077

申请日：2013-04-19

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/336 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/2253 ,  H01L21/761 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78648

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract translation: 用于半导体制造的方法包括在半导体衬底中形成阱。 在阱内形成一个口袋，该口袋具有与阱相反的掺杂极性，以在阱和口袋之间提供p-n结。 在p-n结处产生缺陷，使得p-n结的漏电阻减小。