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公开(公告)号：US10431682B2
公开(公告)日：2019-10-01
申请号：US15693952
申请日：2017-09-01
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC分类号： H01L29/78 , H01L29/66 , H01L21/306 , H01L21/02 , H01L21/324 , H01L29/417
摘要： A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
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公开(公告)号：US10355086B2
公开(公告)日：2019-07-16
申请号：US15181843
申请日：2016-06-14
发明人： Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/84 , H01L29/10 , H01L29/66 , H01L21/306 , H01L29/20 , H01L29/417 , H01L29/78
摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
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公开(公告)号：US20190206868A1
公开(公告)日：2019-07-04
申请号：US16294117
申请日：2019-03-06
发明人： Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L27/092 , H01L29/06 , H01L29/16 , H01L21/8238 , H01L21/033 , H01L21/308 , H01L29/78 , H01L29/165 , H01L29/10 , H01L27/12 , H01L21/84
CPC分类号： H01L27/0924 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/1211 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/7849
摘要： A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
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公开(公告)号：US10032912B2
公开(公告)日：2018-07-24
申请号：US14588221
申请日：2014-12-31
发明人： Pierre Morin , Kangguo Cheng , Jody Fronheiser , Xiuyu Cai , Juntao Li , Shogo Mochizuki , Ruilong Xie , Hong He , Nicolas Loubet
IPC分类号： H01L29/78 , H01L29/16 , H01L29/06 , H01L29/66 , H01L21/8238 , H01L27/092
摘要： A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.
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公开(公告)号：US20180175202A1
公开(公告)日：2018-06-21
申请号：US15890880
申请日：2018-02-07
发明人： Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L29/10 , H01L29/417 , H01L21/306 , H01L29/66
CPC分类号： H01L29/1033 , H01L21/30621 , H01L29/1054 , H01L29/20 , H01L29/41791 , H01L29/66522 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
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公开(公告)号：US09935179B2
公开(公告)日：2018-04-03
申请号：US15472556
申请日：2017-03-29
发明人： Xiuyu Cai , Qing Liu , Kejia Wang , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L29/66 , H01L29/06 , H01L27/088 , H01L21/8234
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0653 , H01L29/41791 , H01L29/66545 , H01L29/6656
摘要： A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
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公开(公告)号：US09859423B2
公开(公告)日：2018-01-02
申请号：US14587655
申请日：2014-12-31
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
IPC分类号： H01L29/165 , H01L29/78 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/41783 , H01L29/6681 , H01L29/7842 , H01L29/7851
摘要： A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.
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公开(公告)号：US09773885B2
公开(公告)日：2017-09-26
申请号：US15471733
申请日：2017-03-28
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L29/66 , H01L21/762 , H01L29/78 , H01L29/06 , H01L21/306
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US09660057B2
公开(公告)日：2017-05-23
申请号：US14307011
申请日：2014-06-17
发明人： Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai , Kejia Wang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/20 , H01L29/205
CPC分类号： H01L29/66795 , H01L29/20 , H01L29/205 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.
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公开(公告)号：US09653579B2
公开(公告)日：2017-05-16
申请号：US14281021
申请日：2014-05-19
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Chun-chen Yeh , Kejia Wang
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8234 , H01L27/088 , H01L29/417
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0653 , H01L29/41791 , H01L29/66545 , H01L29/6656
摘要： A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
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