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    FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS
    71.
    发明申请
    FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS 审中-公开

    公开(公告)号：US20200258779A1

    公开(公告)日：2020-08-13

    申请号：US16860835

    申请日：2020-04-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Juntao Li ,  Zhenxing Bi ,  Dexin Kong

    IPC: H01L21/768 ,  H01L23/522

    Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

    FinFET transistor gate and epitaxy formation
    74.
    发明授权
    FinFET transistor gate and epitaxy formation 有权

    公开(公告)号：US10608121B2

    公开(公告)日：2020-03-31

    申请号：US15846445

    申请日：2017-12-19

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

    IPC: H01L29/788 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28

    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.

    VERTICAL TRANSISTORS WITH MULTIPLE GATE LENGTHS
    75.
    发明申请
    VERTICAL TRANSISTORS WITH MULTIPLE GATE LENGTHS 审中-公开

    公开(公告)号：US20200098863A1

    公开(公告)日：2020-03-26

    申请号：US16684022

    申请日：2019-11-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu ,  Zheng Xu

    IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78

    Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

    Vertical silicon/silicon-germanium transistors with multiple threshold voltages
    80.
    发明授权
    Vertical silicon/silicon-germanium transistors with multiple threshold voltages 有权

    公开(公告)号：US10541176B2

    公开(公告)日：2020-01-21

    申请号：US15947474

    申请日：2018-04-06

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

    Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.

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