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    Semiconductor apparatus capable of error revision using pin extension technique and design method therefor
    72.
    发明申请
    Semiconductor apparatus capable of error revision using pin extension technique and design method therefor 有权
    能够使用引脚扩展技术进行错误修正的半导体装置及其设计方法

    公开(公告)号：US20110140280A1

    公开(公告)日：2011-06-16

    申请号：US12928021

    申请日：2010-12-01

    申请人： Dong-Yun Kim ,  Dong-Hoon Yeo ,  Hyun-Chul Shin ,  Kyung-Ho Kim ,  Byung-Tae Kang ,  Ju-Yong Shin ,  Sung-Chul Lee

    发明人： Dong-Yun Kim ,  Dong-Hoon Yeo ,  Hyun-Chul Shin ,  Kyung-Ho Kim ,  Byung-Tae Kang ,  Ju-Yong Shin ,  Sung-Chul Lee

    IPC分类号： H01L23/48 ,  G06F17/50

    CPC分类号： H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.

    摘要翻译： 半导体装置的半导体装置和设计方法允许使用备用单元进行调试或维修。 半导体装置包括多个金属层。 至少一个修理块执行预定的功能。 备用块能够代替维修块的功能。 并且多个金属层中的至少一个被预先确定为用于错误修正的修复层。 修复块的至少一个销通过第一销延伸连接到修复层，并且备用块的至少一个引脚能够延伸到修复层。 当修理修理块时，修理层和维修块的销延伸被断开，备用块的至少一个引脚通过第二个引脚延伸连接到修复层。

    CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
    73.
    发明申请
    CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
    控制交流干扰编程

    公开(公告)号：US20100103732A1

    公开(公告)日：2010-04-29

    申请号：US12650118

    申请日：2009-12-30

    申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

    发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

    摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

    摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

    OMNIDIRECTIONAL ANTENNA
    74.
    发明申请
    OMNIDIRECTIONAL ANTENNA 有权

    公开(公告)号：US20100026599A1

    公开(公告)日：2010-02-04

    申请号：US12525308

    申请日：2008-01-23

    申请人： Sung-Chul Lee

    发明人： Sung-Chul Lee

    IPC分类号： H01Q1/38

    CPC分类号： H01Q1/36 ,  H01Q9/40

    摘要： The omnidirectional antenna of the present invention comprises a dielectric core 20 of ceramic material which has a longitudinal hole 21 formed in the center; a strip line 30 which is bent to fit the circumference of the dielectric core 20 by a press-forming method and is covered over the upper outer circumference of the dielectric core; a lower cap 40 which is inserted over the bottom end of the dielectric core and has a hole formed at the center of the bottom; a feeder 50 which is passed through and inserted from down to up into the holes formed in the bottom cap and the dielectric core and the top end of which is connected with the strip line 30 on the upper surface of the dielectric core; and a strip line fixing means 60 for combining the lower cap and strip line to the dielectric core.

    摘要翻译： 本发明的全向天线包括陶瓷材料的介质芯20，其具有形成在中心的纵向孔21; 带状线30，其通过压制成型方法弯曲成与电介质芯20的圆周相配合，并且覆盖在电介质芯的上外周上; 下盖40，其插入在电介质芯的底端上并且具有形成在底部中心的孔; 进料器50，其从下到上穿过并插入到形成在底盖和介质芯中的孔中，并且其顶端与介电芯的上表面上的带状线30连接; 以及用于将下盖和带状线组合到电介质芯的带状线固定装置60。

    Semiconductor memory device and fabrication method thereof
    76.
    发明授权
    Semiconductor memory device and fabrication method thereof 有权
    半导体存储器件及其制造方法

    公开(公告)号：US06885070B2

    公开(公告)日：2005-04-26

    申请号：US10259871

    申请日：2002-09-30

    申请人： Sang-Bai Yi ,  Jae-Min Yu ,  Sung-Chul Lee

    发明人： Sang-Bai Yi ,  Jae-Min Yu ,  Sung-Chul Lee

    IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  Y10S257/903

    摘要： In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.

    摘要翻译： 在包括存储单元和外围电路单元的半导体存储器件中，存储单元具有形成在半导体衬底上的第一栅极结构; 第一导电类型的第一杂质区域形成在栅极结构的第一侧上的衬底中; 以及形成在所述栅极结构的第二侧上的所述衬底中的第二杂质区域，所述第二杂质区域包括：第一导电类型的第三杂质区域，第三杂质区域和第三杂质区域之间的第一导电类型的第四杂质区域， 栅极结构的第二侧和与第四杂质区相邻形成的第二导电类型的晕圈离子区。

    Omnidirectional antenna
    77.
    发明授权
    Omnidirectional antenna 有权
    全向天线

    公开(公告)号：US08803752B2

    公开(公告)日：2014-08-12

    申请号：US12525308

    申请日：2008-01-23

    申请人： Sung-Chul Lee

    发明人： Sung-Chul Lee

    IPC分类号： H01Q1/36 ,  H01Q9/06

    CPC分类号： H01Q1/36 ,  H01Q9/40

    摘要： The omnidirectional antenna of the present invention comprises a dielectric core 20 of ceramic material which has a longitudinal hole 21 formed in the center; a strip line 30 which is bent to fit the circumference of the dielectric core 20 by a press-forming method and is covered over the upper outer circumference of the dielectric core; a lower cap 40 which is inserted over the bottom end of the dielectric core and has a hole formed at the center of the bottom; a feeder 50 which is passed through and inserted from down to up into the holes formed in the bottom cap and the dielectric core and the top end of which is connected with the strip line 30 on the upper surface of the dielectric core; and a strip line fixing means 60 for combining the lower cap and strip line to the dielectric core.

    摘要翻译： 本发明的全向天线包括陶瓷材料的介质芯20，其具有形成在中心的纵向孔21; 带状线30，其通过压制成型方法弯曲成与电介质芯20的圆周相配合，并且覆盖在电介质芯的上外周上; 下盖40，其插入在电介质芯的底端上并且具有形成在底部中心的孔; 进料器50，其从下到上穿过并插入到形成在底盖和介质芯中的孔中，并且其顶端与介电芯的上表面上的带状线30连接; 以及用于将下盖和带状线组合到电介质芯的带状线固定装置60。

    CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
    78.
    发明申请
    CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
    控制交流干扰编程

    公开(公告)号：US20120294103A1

    公开(公告)日：2012-11-22

    申请号：US13569442

    申请日：2012-08-08

    申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

    发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

    IPC分类号： G11C7/12

    CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

    摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

    摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。