公开(公告)号：US09726723B2

公开(公告)日：2017-08-08

申请号：US14825298

申请日：2015-08-13

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Ronald E. Fuhs

IPC: G11C29/00 ,  G01R31/3177 ,  G06F11/26 ,  G06F11/22

CPC classification number: G01R31/3177 ,  G06F11/2236 ,  G06F11/26

Abstract: A method for scanning a partially functional chip. The method may include applying a failed core map to the partially functional chip, bypassing at least one failed core scan chain, based on contents of the failed core map. The method may also include performing comparisons of scan status information to the failed core map and inhibiting movement of scan data of at least one failed core, based on results of the comparisons.

公开(公告)号：US09551747B2

公开(公告)日：2017-01-24

申请号：US14568312

申请日：2014-12-12

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3172 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318594

Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

公开(公告)号：US20160216324A1

公开(公告)日：2016-07-28

申请号：US14697032

申请日：2015-04-27

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer

IPC: G01R31/3177

CPC classification number: G01R31/318563 ,  G01R31/318558

Abstract: A method and system for implementing enhanced scan chain diagnostics via a bypass multiplexing structure. A full scan chain structure is partitioned into a plurality of separate chains, such as three separate partitioned chains, with bypass multiplexers for implementing enhanced scan chain diagnostics. Each of the separate partitioned chains includes bypass multiplexers with independent controls enabling scan data being routed through multiple different independent scan paths, potentially bypassing failing latches. The information acquired from a combination of full scans and partitioned scans is used for scan failure isolation to enable pinpoint identification of stuck-at-zero (SA0) and stuck-at-one (SA1) faults in the scan chain.

公开(公告)号：US09378318B2

公开(公告)日：2016-06-28

申请号：US14283332

申请日：2014-05-21

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Mary P. Kusko

IPC: G06F17/50 ,  G06F19/00 ,  G01R31/00 ,  G21K5/00 ,  G03F1/00 ,  G01R31/20 ,  G06F21/00

CPC classification number: G06F17/5072 ,  G01R31/20 ,  G03F1/00 ,  G06F17/5045 ,  G06F17/5081 ,  G06F21/00 ,  G06F2217/12 ,  G06F2217/14 ,  G21K5/00

Abstract: A method of masking scan channels in a semiconductor chip includes storing, in first and second memories of a first mask logic, first and second channel mask enable decodes for first and second masks that mask first and second scan channels of a circuit under test; receiving at least three channel enable signals on three respective enable pins to produce a channel mask enable encode; comparing the channel mask enable encode to the stored first and second enable decodes; and masking the first or second scan channel when the channel mask enable encode respectively matches the first or second channel mask enable decode.

Abstract translation: 屏蔽半导体芯片中的扫描通道的方法包括在第一和第二存储器中存储第一和第二通道屏蔽使能解码用于屏蔽被测电路的第一和第二扫描通道的第一和第二掩模; 在三个相应的使能引脚上接收至少三个通道使能信号以产生通道屏蔽使能编码; 将所述信道掩码使能编码与所存储的第一和第二使能解码进行比较; 以及当所述信道掩码使能编码分别与所述第一或第二信道掩码使能解码匹配时，掩蔽所述第一或第二扫描信道。

公开(公告)号：US09297856B2

公开(公告)日：2016-03-29

申请号：US14060744

申请日：2013-10-23

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Mary P. Kusko ,  Cédric Lichtenau

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318547 ,  G01R31/31703

Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.

Abstract translation: 一种用于实现用于测试时间减少的多输入签名寄存器（MISR）压缩的方法和电路，以及提供主题电路所在的设计结构。 MISR压缩电路包括第一MISR，设置有第一MISR的第二MISR和压缩器，用于压缩位于第一MISR和第二MISR之一之间以及第二MISR之后的MISR数据。

公开(公告)号：US09201117B2

公开(公告)日：2015-12-01

申请号：US13887674

申请日：2013-05-06

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318544

Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.

Abstract translation: 公开了使用IEEE TM 1149.1边界扫描锁存器重新路由功能路径的IO结构，方法和装置。 使用IEEE TM 1149.1边界扫描锁存器的芯片的方法可以包括使用IEEE TM 1149.1边界扫描锁存器来测试芯片上的IO。 该方法还可以包括使用存储在IEEE TM 1149.1边界扫描锁存器中的信息来以功能模式在故障路径周围路由信号。

公开(公告)号：US09134375B1

公开(公告)日：2015-09-15

申请号：US14283344

申请日：2014-05-21

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Mary P. Kusko

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G06F11/263

Abstract: A method of creating a scan pattern test file for testing hierarchal test blocks (HTBs) of scan channels on a semiconductor chip is described. The method includes determining a maximum number of channel mask enable encodes on the semiconductor chip. A maximum number of channel mask enable encodes used for the first HTB and the second HTB are determined. A plurality of test patterns used to test the first and the second HTB into one or more mask sets dependent on the number of masks each test pattern needs are sorted. The test patterns of the mask sets of the first and second HTB to be performed in a same test pattern are combined. The number of masks per scan cycle of the combined mask sets is no more than the maximum number of channel mask enable encodes on the semiconductor chip and there is no scan slice overlap.

公开(公告)号：US20150254387A1

公开(公告)日：2015-09-10

申请号：US14196448

申请日：2014-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steven M. Douskey ,  Mary P. Kusko

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G01R31/20 ,  G03F1/00 ,  G06F17/5045 ,  G06F17/5081 ,  G06F21/00 ,  G06F2217/12 ,  G06F2217/14 ,  G21K5/00

Abstract: A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first comparator and a second comparator. The first and second comparator compare the respective channel mask enable decodes to the channel mask enable encode. The comparators signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable encode.

Abstract translation: 半导体芯片包括第一掩模逻辑。 第一掩模逻辑包括掩蔽相应的第一扫描通道输出和第二扫描通道输出的第一掩模和第二掩模。 第一掩模逻辑包括至少三个使能引脚，其接收相应的使能信号。 三个使能信号产生通道掩码使能编码。 第一掩模逻辑包括存储第一掩模的第一通道屏蔽使能解码的第一存储器和存储第二掩码的第二通道掩码使能解码的第二存储器。 第一掩模逻辑包括第一比较器和第二比较器。 第一和第二比较器将相应的通道屏蔽使能解码器与通道掩码使能编码进行比较。 当相应的通道屏蔽允许解码与通道屏蔽使能编码匹配时，比较器发出相应的屏蔽来掩蔽相应的扫描通道。

公开(公告)号：US09103879B2

公开(公告)日：2015-08-11

申请号：US13778812

申请日：2013-02-27

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Ryan A. Fitch ,  Michael J. Hamilton ,  Amanda R. Kaufer

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G01R31/318563

Abstract: An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).

Abstract translation: 提供了一种用于将输入引脚切换到扫描通道以增加测试覆盖率的装置和方法。 在一个实施例中，扫描系统将少量输入引脚连接到多个扫描通道，使得可以有选择地切换输入引脚。 输入引脚可以传输独立的测试向量，以测试半导体芯片上的大量测试区域。 扫描系统可以包括诸如多路复用器（MUX）之类的开关装置。

公开(公告)号：US20150089312A1

公开(公告)日：2015-03-26

申请号：US14109258

申请日：2013-12-17

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Mary P. Kusko ,  Cedric Lichtenau

IPC: G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318566

Abstract: A system and method of testing a chip is disclosed. The method may include scanning input data into a first scan channel serially connected to a second scan channel. The scan channels may comprise a plurality of scannable latches, configured to scan input data to apply to logic circuits on the chip and to receive outputs from the logic circuits. The method may include outputting a data from the first scan channel to a first rotator. The method may include creating adjustment data using the data from the first scan channel by the rotator and transmitting of the adjustment data to a second XOR on the second scan channel. The method may exclusive or the adjustment data from the first rotator with an output of the first XOR of the second scan channel, wherein the first XOR hashes output data from the scannable latches of the second scan channel.