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公开(公告)号：US09312578B2
公开(公告)日：2016-04-12
申请号：US14039275
申请日：2013-09-27
申请人： Lithium Energy Japan
CPC分类号： H01M10/48 , G01R31/1263 , G01R31/20 , G01R31/3627 , G01R31/3644 , H01M2/1016 , H01M2/1077 , H01M10/482
摘要： A battery module includes a metal casing and a battery cell accommodated in the casing. The casing is provided on its outer surface with an insulation layer and a conductive portion.
摘要翻译： 电池模块包括容纳在壳体中的金属壳体和电池单元。 壳体在其外表面上设置有绝缘层和导电部分。
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2.发明申请公开(公告)号：US20140376174A1
公开(公告)日：2014-12-25
申请号：US13922136
申请日：2013-06-19
发明人： David Lee Dean , Dennis Bennett , Robert W. Ellis
IPC分类号： G06F1/20
CPC分类号： G06F1/20 , G01R31/20 , G06F1/186 , H05K1/118 , H05K1/14 , H05K1/144 , H05K1/148 , H05K5/0026 , H05K7/20 , H05K2201/042 , H05K2201/058 , Y10T29/49002
摘要： An electronic assembly and method of manufacturing includes: an airflow bracket having a circular rail and an airflow tab, the airflow bracket electrically coupling the circular rail and the airflow tab; a top board attached to the circular rail for electrically coupling the top board and the circular rail; and a bottom board attached to the circular rail for electrically coupling the top board and the circular rail, the bottom board positioned to form a thermal channel between the top board and the bottom board for directing air through a vent opening of the circular rail.
摘要翻译： 电子组件和制造方法包括：具有圆形轨道和气流接头的气流支架，气流支架电连接圆形轨道和气流接头; 连接到圆形导轨的顶板，用于电连接顶板和圆形导轨; 以及附接到圆形导轨的底板，用于电连接顶板和圆形导轨，底板被定位成在顶板和底板之间形成热通道，用于引导空气通过圆形导轨的通风口。
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公开(公告)号：US20150254390A1
公开(公告)日：2015-09-10
申请号：US14283332
申请日：2014-05-21
发明人： Steven M. Douskey , Mary P. Kusko
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G01R31/20 , G03F1/00 , G06F17/5045 , G06F17/5081 , G06F21/00 , G06F2217/12 , G06F2217/14 , G21K5/00
摘要： A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first comparator and a second comparator. The first and second comparator compare the respective channel mask enable decodes to the channel mask enable encode. The comparators signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable encode.
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公开(公告)号：US09046564B1
公开(公告)日：2015-06-02
申请号：US13568272
申请日：2012-08-07
申请人： Joseph Alan Griffin
发明人： Joseph Alan Griffin
IPC分类号： G01R31/20
CPC分类号： G01R31/20 , G01R31/006
摘要： A circuit testing device for providing a number of features to assist in testing electrical circuits in a vehicle. The circuit testing device generally includes a housing having a plurality of testing components positioned thereon and therein. The housing generally includes a light source such as an LED for assisting in illuminating dark spaces. The housing also includes a probe for closing connections and an incandescent bulb for testing purposes. A polarity switch is provided to quickly and easily reverse polarity of the probe. A circuit breaker and circuit activation switch are also provided. By utilizing the present invention, circuit integrity as well as electrical testing of various components (both high voltage and low voltage) of a vehicle may be efficiently performed.
摘要翻译： 一种用于提供许多特征以帮助测试车辆中的电路的电路测试装置。 电路测试装置通常包括具有定位在其上和其中的多个测试部件的壳体。 壳体通常包括诸如用于辅助照明暗处的LED的光源。 外壳还包括用于闭合连接的探头和用于测试目的的白炽灯泡。 提供极性开关以快速和容易地反转探头的极性。 还提供了一种断路器和电路启动开关。 通过利用本发明，可以有效地执行车辆的各种部件（高压和低压）的电路完整性以及电气测试。
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5.发明申请公开(公告)号：US20040120098A1
公开(公告)日：2004-06-24
申请号：US10717639
申请日：2003-11-21
IPC分类号： H01G004/32
CPC分类号： H01G2/20 , G01R31/20 , H05K1/0256 , H05K1/162 , H05K2201/0761 , H05K2201/09309 , H05K2203/0143 , H05K2203/162
摘要： The present invention provides a technique which permits the withstand voltage measurement of a laminate web for capacitor layer manufactured by a continuous laminating method in a roll state wound around a core tube. The invention provides a roll of laminate for capacitor layer which is obtained by manufacturing a laminate web for capacitor layer by laminating a first electrically conductive layer, a dielectric layer and a second electrically conductive layer and winding this laminate web for capacitor layer from a start end side to a terminal end side thereof around a core tube. In the laminate web for capacitor layer 1a to be wound around the core tube 2, the in-plane laminating arrangement of the first electrically conductive layer 3, the second electrically conductive layer 5 and the dielectric layer 4 is contrived, and by superposing an insulating resin film F on one side of this laminate web for capacitor layer and simultaneously winding this insulating resin film to make the laminate web for capacitor layer in a roll state, whereby a roll of laminate web for capacitor layer for withstand voltage inspection in which electrical insulation between layers overlapping each other is formed. The invention also provides a method of performing withstand voltage inspection which involves partially removing interlayer dielectric means of the laminate web for capacitor layer 1a positioned in the periphery of the roll of laminate web for withstand voltage inspection and performing the inspection using the exposed first and second electrically conductive layers.
摘要翻译： 本发明提供了一种技术，其允许通过卷绕在芯管周围的卷状连续层压法制造的用于电容器层的层叠幅材的耐压测量。 本发明提供了一种用于电容器层的层叠体，其通过层压第一导电层，电介质层和第二导电层而制造用于电容器层的层叠幅材而获得，并且从起始端卷绕用于电容器层的层叠幅材 一侧到其末端侧围绕芯管。 在卷绕在芯管2上的电容器层1a的叠层织物中，设计第一导电层3，第二导电层5和电介质层4的面内层叠布置，并且通过叠加绝缘 树脂膜F，用于电容器层的一侧，同时卷绕该绝缘树脂膜，制成卷状状的电容器层的层压纤维网，由此可以进行耐电压检查的电容层用层叠纤维卷，其中电绝缘 形成彼此重叠的层。 本发明还提供了一种执行耐电压检查的方法，该方法包括部分去除位于层叠幅材卷的周边的电容器层1a的层压纤维网的层间绝缘装置，用于耐电压检查，并使用暴露的第一和第二 导电层。
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公开(公告)号：US09378318B2
公开(公告)日：2016-06-28
申请号：US14283332
申请日：2014-05-21
发明人： Steven M. Douskey , Mary P. Kusko
CPC分类号： G06F17/5072 , G01R31/20 , G03F1/00 , G06F17/5045 , G06F17/5081 , G06F21/00 , G06F2217/12 , G06F2217/14 , G21K5/00
摘要： A method of masking scan channels in a semiconductor chip includes storing, in first and second memories of a first mask logic, first and second channel mask enable decodes for first and second masks that mask first and second scan channels of a circuit under test; receiving at least three channel enable signals on three respective enable pins to produce a channel mask enable encode; comparing the channel mask enable encode to the stored first and second enable decodes; and masking the first or second scan channel when the channel mask enable encode respectively matches the first or second channel mask enable decode.
摘要翻译： 屏蔽半导体芯片中的扫描通道的方法包括在第一和第二存储器中存储第一和第二通道屏蔽使能解码用于屏蔽被测电路的第一和第二扫描通道的第一和第二掩模; 在三个相应的使能引脚上接收至少三个通道使能信号以产生通道屏蔽使能编码; 将所述信道掩码使能编码与所存储的第一和第二使能解码进行比较; 以及当所述信道掩码使能编码分别与所述第一或第二信道掩码使能解码匹配时，掩蔽所述第一或第二扫描信道。
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公开(公告)号：US20150254387A1
公开(公告)日：2015-09-10
申请号：US14196448
申请日：2014-03-04
发明人： Steven M. Douskey , Mary P. Kusko
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G01R31/20 , G03F1/00 , G06F17/5045 , G06F17/5081 , G06F21/00 , G06F2217/12 , G06F2217/14 , G21K5/00
摘要： A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output. The first mask logic includes at least three enable pins that receive respective enable signals. The three enable signals produce a channel mask enable encode. The first mask logic includes a first memory that stores a first channel mask enable decode for the first mask and a second memory that stores a second channel mask enable decode for the second mask. The first mask logic includes a first comparator and a second comparator. The first and second comparator compare the respective channel mask enable decodes to the channel mask enable encode. The comparators signal respective masks to mask the respective scan channel when the respective channel mask enable decode matches the channel mask enable encode.
摘要翻译： 半导体芯片包括第一掩模逻辑。 第一掩模逻辑包括掩蔽相应的第一扫描通道输出和第二扫描通道输出的第一掩模和第二掩模。 第一掩模逻辑包括至少三个使能引脚，其接收相应的使能信号。 三个使能信号产生通道掩码使能编码。 第一掩模逻辑包括存储第一掩模的第一通道屏蔽使能解码的第一存储器和存储第二掩码的第二通道掩码使能解码的第二存储器。 第一掩模逻辑包括第一比较器和第二比较器。 第一和第二比较器将相应的通道屏蔽使能解码器与通道掩码使能编码进行比较。 当相应的通道屏蔽允许解码与通道屏蔽使能编码匹配时，比较器发出相应的屏蔽来掩蔽相应的扫描通道。
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公开(公告)号：US09128119B2
公开(公告)日：2015-09-08
申请号：US13853525
申请日：2013-03-29
发明人： Waleed M. Said
CPC分类号： G01R1/0416 , G01R31/008 , G01R31/1227 , G01R31/20
摘要： An electronics system module includes a primary electrical circuit including input connectors and output connectors and a filter circuit connected between the primary electrical circuit and ground. The module also includes a switch element connected between the primary electrical circuit and ground. The switch element is configured to be engaged by a test connector to open the switch to disconnect the primary electrical circuit from ground. The test connector includes electrical connectors configured to connect to the input connectors and the output connectors of the primary electrical circuit. The switch element is configured to automatically close based on the test connector being disengaged from the switch element.
摘要翻译： 电子系统模块包括主电路，其包括输入连接器和输出连接器以及连接在主电路和地之间的滤波电路。 该模块还包括连接在主电路和地之间的开关元件。 开关元件被配置为由测试连接器接合以打开开关以将主电路与地断开。 测试连接器包括被配置为连接到主电路的输入连接器和输出连接器的电连接器。 开关元件被配置为基于从开关元件脱离的测试连接器自动关闭。
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9.发明授权公开(公告)号：US06903916B2
公开(公告)日：2005-06-07
申请号：US10717639
申请日：2003-11-21
CPC分类号： H01G2/20 , G01R31/20 , H05K1/0256 , H05K1/162 , H05K2201/0761 , H05K2201/09309 , H05K2203/0143 , H05K2203/162
摘要： The present invention provides a technique which permits the withstand voltage measurement of a laminate web for capacitor layer manufactured by a continuous laminating method in a roll state wound around a core tube. The invention provides a roll of laminate for capacitor layer which is obtained by manufacturing a laminate web for capacitor layer by laminating a first electrically conductive layer, a dielectric layer and a second electrically conductive layer and winding this laminate web for capacitor layer from a start end side to a terminal end side thereof around a core tube. In the laminate web for capacitor layer 1a to be wound around the core tube 2, the in-plane laminating arrangement of the first electrically conductive layer 3, the second electrically conductive layer 5 and the dielectric layer 4 is contrived, and by superposing an insulating resin film F on one side of this laminate web for capacitor layer and simultaneously winding this insulating resin film to make the laminate web for capacitor layer in a roll state, whereby a roll of laminate web for capacitor layer for withstand voltage inspection in which electrical insulation between layers overlapping each other is formed. The invention also provides a method of performing withstand voltage inspection which involves partially removing interlayer dielectric means of the laminate web for capacitor layer 1a positioned in the periphery of the roll of laminate web for withstand voltage inspection and performing the inspection using the exposed first and second electrically conductive layers.
摘要翻译： 本发明提供了一种技术，其允许通过卷绕在芯管周围的卷状连续层压法制造的用于电容器层的层叠幅材的耐压测量。 本发明提供了一种用于电容器层的层叠体，其通过层压第一导电层，电介质层和第二导电层而制造用于电容器层的层叠幅材而获得，并且从起始端卷绕用于电容器层的层叠幅材 一侧到其末端侧围绕芯管。 在用于电容器层1a的层叠网中，缠绕在芯管2上，设计第一导电层3，第二导电层5和电介质层4的面内层叠布置，并且通过将 绝缘树脂膜F在用于电容器层的该层叠纤维网的一侧上，并同时卷绕该绝缘树脂膜，以使卷绕状态的电容器层的层叠幅材成为卷状状的电容器层用层叠纤维网， 形成彼此重叠的层之间的绝缘。 本发明还提供了一种执行耐电压检查的方法，该方法包括部分去除位于层叠幅材卷的周边的电容器层1a的叠层网状物的层间绝缘装置，用于耐电压检查，并使用暴露的第一和第 第二导电层。
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10.发明授权公开(公告)号：US12055577B2
公开(公告)日：2024-08-06
申请号：US17956859
申请日：2022-09-30
发明人： Man Xu , Sunjiaxing Wei , Yangtao Peng , Yunshun Peng
CPC分类号： G01R31/1272 , G01R1/0408 , G01R31/20
摘要： Provided are an electrical tree test device for a silicone rubber material for a cable accessory and a method for preparing a sample. The method includes: adding a semi-conductive silicone rubber into xylene, performing spraying on a surface of a silicone rubber insulation sample sheet, performing a curing processing, cutting the sample sheet into a high-voltage electrode with a triangular longitudinal section end, then adhering the high-voltage electrode on the surface of the silicone rubber insulation sample sheet, and performing a high temperature vulcanization to obtain a silicon rubber sample sheet; placing the silicon rubber sample sheet into a mold, injecting a high temperature vulcanizable liquid silicone rubber mixture, and performing the high temperature vulcanization, to obtain a sample; and performing cutting at a position distanced from a tip of the high-voltage electrode by 2 mm, and adhering a ground electrode of a flat plate-like structure at the cross section.
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