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    Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode
    71.
    发明授权
    Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode 有权
    双金属CMOS晶体管与硅 - 金属硅堆叠栅电极

    公开(公告)号：US07018887B1

    公开(公告)日：2006-03-28

    申请号：US10788281

    申请日：2004-03-01

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L21/8238

    CPC classification number: H01L21/823842

    Abstract: A method of forming dual metal CMOS transistors includes forming a first silicon layer on a gate dielectric layer provided on a substrate. A first metal layer is formed on the NMOS device areas. A second metal layer is formed on the PMOS device areas. These first and second metal layers consist of different metals. A second silicon layer is deposited on the first and second metal layers. A dry etching technique is performed to etch the second silicon layer, the first and second metal layers, and the first silicon layer. The dry etching stops on the gate dielectric layer, thereby forming gate electrodes. The first and second metal layers are reacted with the first and second silicon layers to form suicides in the gate electrodes.

    Abstract translation: 形成双金属CMOS晶体管的方法包括在设置在基板上的栅介质层上形成第一硅层。 在NMOS器件区域上形成第一金属层。 在PMOS器件区域上形成第二金属层。 这些第一和第二金属层由不同的金属组成。 第二硅层沉积在第一和第二金属层上。 执行干蚀刻技术以蚀刻第二硅层，第一和第二金属层以及第一硅层。 干蚀刻停止在栅介质层上，从而形成栅电极。 第一和第二金属层与第一和第二硅层反应，以在栅电极中形成自杀。

    Strained silicon MOSFET having improved thermal conductivity and method for its fabrication
    72.
    发明授权
    Strained silicon MOSFET having improved thermal conductivity and method for its fabrication 失效
    具有改进的导热性的应变硅MOSFET及其制造方法

    公开(公告)号：US07012007B1

    公开(公告)日：2006-03-14

    申请号：US10658479

    申请日：2003-09-09

    Applicant: Jung-Suk Goo ,  Qi Xiang ,  James Pan

    Inventor： Jung-Suk Goo ,  Qi Xiang ,  James Pan

    IPC: H01L21/336

    CPC classification number: H01L29/665 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

    Abstract: A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal conductivity material is preferably silicon carbide, and the isolations preferably extend through the silicon germanium layer to contact an underlying silicon layer so as to conduct thermal energy from the active region to the silicon layer.

    Abstract translation: 应变硅MOSFET在沟槽隔离中采用高导热绝缘材料，以消散MOSFET中产生的热能，并避免由于下层硅锗层导热性差导致的自发热。 高导热性材料优选为碳化硅，并且隔离优选延伸穿过硅锗层以接触下面的硅层，以便将热能从有源区传导到硅层。

    Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same
    74.
    发明申请
    Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same 有权
    具有可调栅电极功能的双金属CMOS晶体管及其制作方法

    公开(公告)号：US20050245016A1

    公开(公告)日：2005-11-03

    申请号：US10833073

    申请日：2004-04-28

    Applicant: James Pan ,  Ming-Ren Lin

    Inventor： James Pan ,  Ming-Ren Lin

    IPC: H01L21/28 ,  H01L21/8238

    CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823842

    Abstract: A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.

    Abstract translation: 双金属CMOS布置及其制造方法提供了形成在衬底上的衬底和多个NMOS器件和PMOS器件。 多个NMOS器件和PMOS器件中的每一个具有栅电极。 每个NMOS栅极包括衬底上的第一硅化物区域和第一硅化物区域上的第一金属区域。 NMOS栅电极的第一硅化物区域由具有接近硅导带的功函数的第一硅化物组成。 每个PMOS栅极电极包括衬底上的第二硅化物区域和第二硅化物区域上的第二金属区域。 PMOS栅电极的第二硅化物区域由具有接近硅的价带的功函数的第二硅化物组成。

    Method of processing selected surfaces in a semiconductor process chamber based on a temperature differential between surfaces
    79.
    发明申请
    Method of processing selected surfaces in a semiconductor process chamber based on a temperature differential between surfaces 失效
    基于表面之间的温度差处理在半导体处理室中选择的表面的方法

    公开(公告)号：US20050150448A1

    公开(公告)日：2005-07-14

    申请号：US11050998

    申请日：2005-02-04

    Applicant: James Pan

    Inventor： James Pan

    IPC: C23C16/44 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  G01J5/00

    CPC classification number: C23C16/4405 ,  Y10S438/905

    Abstract: The present invention relates to a method of processing selected surfaces in a semiconductor process chamber by creating a temperature differential between the selected surfaces and contacting the surfaces with a reactant that preferentially react with a surface at one end of the temperature differential relative to the other selected surface(s). More particularly, the invention relates to the use of nitrogen trifluoride (NF3) gas for in situ cleaning of cold wall process chambers such as Rapid thermal Chemical Vaporization (“RTCVD”) systems.

    Abstract translation: 本发明涉及一种通过在所选择的表面之间产生温度差并使表面与相对于另一个所选择的表面的温度差的一端优先与表面反应的反应物接触来处理半导体处理室中的选定表面的方法 表面。 更具体地说，本发明涉及三氟化氮（NF 3 N 3）气体用于诸如快速热化学气化（“RTCVD”）系统的冷壁处理室的原位清洁的用途。

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