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91 条记录 (耗时 0.05 秒)

    Active impedance compensation
    71.
    发明授权
    Active impedance compensation 失效
    有源阻抗补偿

    公开(公告)号：US06530062B1

    公开(公告)日：2003-03-04

    申请号：US09523520

    申请日：2000-03-10

    申请人： Haw-Jyh Liaw ,  Donald V. Perino ,  Pak Shing Chau ,  Kevin S. Donnelly

    发明人： Haw-Jyh Liaw ,  Donald V. Perino ,  Pak Shing Chau ,  Kevin S. Donnelly

    IPC分类号： G06F1750

    CPC分类号： G06F13/4086

    摘要： Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.

    摘要翻译： 有源阻抗补偿通过与系统从设备之间的连接电路和阻抗平衡通道相关联的可变电容器元件在总线系统中完成。 可变电容器元件可以使用通过用遥测信号主动地运行通道所确定的控制值进行编程，并且评估指示通道上的阻抗不连续性的结果信号反射。

    Transceiver with selectable data rate
    74.
    发明授权
    Transceiver with selectable data rate 有权
    收发器具有可选数据速率

    公开(公告)号：US07190754B1

    公开(公告)日：2007-03-13

    申请号：US10026371

    申请日：2001-12-24

    申请人： Kun-Yung K. Chang ,  Kevin S. Donnelly

    发明人： Kun-Yung K. Chang ,  Kevin S. Donnelly

    IPC分类号： H03D3/24 ,  H04L7/00

    CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

    摘要： An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

    摘要翻译： 一种具有可选数据速率时钟数据恢复（CDR）电路和可选数据速率发射电路的集成电路装置。 CDR电路包括在第一时钟信号的周期期间捕获输入信号的多个采样的接收电路。 选择电路耦合到接收电路，以根据接收数据速率选择信号选择多个采样中的一个作为输入信号的第一选定采样，并将多个样本中的另一个作为第二选定采样 的输入信号。 相位控制电路被耦合以接收输入信号的第一和第二选定采样，并且包括用于比较所选择的采样以确定第一时钟信号是否导通或滞后输入信号的转换的电路。 发送电路包括串行电路，用于接收并行的一组位，并且响应于第一时钟信号而将该组比特顺序输出到输出驱动器。 选择电路根据发送数据速率选择信号选择出站数据值内的数据位，以形成在串行化电路内接收的并行的一组位。 当发送数据速率选择信号处于第一状态时，选择出站数据值内的比特以实现第一数据速率，并且当发送数据速率选择信号处于第二状态时获得第二数据速率。

    At frequency phase shifting circuit for use in a quadrature clock generator
    75.
    再颁专利
    At frequency phase shifting circuit for use in a quadrature clock generator 有权
    用于正交时钟发生器的频率移相电路

    公开(公告)号：USRE37452E1

    公开(公告)日：2001-11-20

    申请号：US09654861

    申请日：2000-09-01

    申请人： Kevin S. Donnelly ,  Pak Shing Chau

    发明人： Kevin S. Donnelly ,  Pak Shing Chau

    IPC分类号： H03H1116

    CPC分类号： H03L7/0812 ,  H03H11/18 ,  H03K5/133 ,  H03K5/151 ,  H03K2005/00208

    摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

    摘要翻译： 可用作正交时钟发生器的一部分的移相电路。 相移电路包括耦合以接收输入参考信号的三角波发生器。 三角波发生器响应于输入参考信号输出一对互补三角波信号。 具有一对输入的比较器被耦合以接收该对互补三角波信号。 响应于一对互补三角波信号之间的比较，比较器输出与输入参考信号具有预定相位关系的输出信号。

    Zero power reset circuit for low voltage CMOS circuits
    76.
    发明授权
    Zero power reset circuit for low voltage CMOS circuits 失效
    用于低压CMOS电路的零功率复位电路

    公开(公告)号：US6107847A

    公开(公告)日：2000-08-22

    申请号：US000717

    申请日：1997-12-30

    申请人： Mark G. Johnson ,  Kevin S. Donnelly ,  Clemenz L. Portmann

    发明人： Mark G. Johnson ,  Kevin S. Donnelly ,  Clemenz L. Portmann

    IPC分类号： H03K3/356 ,  H03K17/22 ,  H03L7/00

    CPC分类号： H03K17/223 ,  H03K3/356008

    摘要： A pulse generating circuit that includes an unbalanced latch and a feedback circuit. The unbalanced latch is configured to generate a latch signal having a predetermined state in response to application of power to the circuit. The feedback circuit is coupled in a negative feedback arrangement with the unbalanced latch and generates a pulse signal for a predetermined period of time in response to the latch signal.

    摘要翻译： 一种包括不平衡锁存器和反馈电路的脉冲发生电路。 不平衡锁存器被配置为响应于向电路施加电力而产生具有预定状态的锁存信号。 反馈电路以负反馈装置与不平衡锁存器耦合，并响应于锁存信号产生预定时间段的脉冲信号。

    At frequency phase shifting circuit for use in a quadrature clock generator
    77.
    发明授权
    At frequency phase shifting circuit for use in a quadrature clock generator 失效
    用于正交时钟发生器的频率移相电路

    公开(公告)号：US5808498A

    公开(公告)日：1998-09-15

    申请号：US891128

    申请日：1997-07-10

    申请人： Kevin S. Donnelly ,  Pak Shing Chau

    发明人： Kevin S. Donnelly ,  Pak Shing Chau

    IPC分类号： H03K5/15 ,  H03H11/18 ,  H03K5/00 ,  H03K5/13 ,  H03K5/151 ,  H03L7/081 ,  H03H11/16

    CPC分类号： H03L7/0812 ,  H03H11/18 ,  H03K5/133 ,  H03K5/151 ,  H03K2005/00208

    摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

    摘要翻译： 可用作正交时钟发生器的一部分的移相电路。 相移电路包括耦合以接收输入参考信号的三角波发生器。 三角波发生器响应于输入参考信号输出一对互补三角波信号。 具有一对输入的比较器被耦合以接收该对互补三角波信号。 响应于一对互补三角波信号之间的比较，比较器输出与输入参考信号具有预定相位关系的输出信号。

    Transceiver with selectable data rate
    80.
    发明授权
    Transceiver with selectable data rate 有权
    收发器具有可选数据速率

    公开(公告)号：US08040988B2

    公开(公告)日：2011-10-18

    申请号：US11685017

    申请日：2007-03-12

    申请人： Kun-Yung K. Chang ,  Kevin S. Donnelly

    发明人： Kun-Yung K. Chang ,  Kevin S. Donnelly

    IPC分类号： H04L7/00 ,  H04L7/02 ,  H03L7/00

    CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

    摘要： An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal. A select circuit selects, according to a transmit data rate select signal, data bits within an outbound data value to form the parallel set of bits received within the serializing circuit. Bits within the outbound data value are selected to achieve a first data rate when the transmit data rate select signal is in a first state, and to achieve a second data rate when the transmit data rate select signal is in a second state.

    摘要翻译： 一种具有可选数据速率时钟数据恢复（CDR）电路和可选数据速率发射电路的集成电路装置。 CDR电路包括在第一时钟信号的周期期间捕获输入信号的多个采样的接收电路。 选择电路耦合到接收电路，以根据接收数据速率选择信号选择多个采样中的一个作为输入信号的第一选定采样，并将多个样本中的另一个作为第二选定采样 的输入信号。 相位控制电路被耦合以接收输入信号的第一和第二选定采样，并且包括用于比较所选择的采样以确定第一时钟信号是否导通或滞后输入信号的转换的电路。 发送电路包括串行电路，用于接收并行的一组位，并且响应于第一时钟信号而将该组比特顺序地输出到输出驱动器。 选择电路根据发送数据速率选择信号选择出站数据值内的数据位，以形成在串行化电路内接收的并行的一组位。 当发送数据速率选择信号处于第一状态时，选择出站数据值内的比特以实现第一数据速率，并且当发送数据速率选择信号处于第二状态时获得第二数据速率。