公开(公告)号：US20070028035A1

公开(公告)日：2007-02-01

申请号：US11493904

申请日：2006-07-27

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： A storage device enabling realization of a new storage configuration enabling apparent elimination of the overhead and enabling high speed access all the time particularly when constructing a high parallel configured high speed flash memory system, that is, a storage device having a flash memory as a main storage and having the function of rewriting at least a partial region of the flash memory by additional writing update data in an empty region and invalidating original data and, at the time of standby of the device where there is no access from the outside, performing processing for automatically restoring the invalidated region to an empty region, and a computer system and a storage system using the same.

摘要翻译： 一种存储装置，其能够实现新的存储配置，从而明显地消除开销并且始终实现高速访问，特别是在构建高并行配置的高速闪速存储器系统时，即具有闪速存储器作为主要的存储装置 存储并且具有通过在空白区域中附加写入更新数据来重新写入闪速存储器的至少部分区域的功能，并且使原始数据无效，并且在不存在来自外部的设备的待机时，执行处理 用于将无效区域自动恢复到空白区域，以及使用该区域的计算机系统和存储系统。

公开(公告)号：US20050259479A1

公开(公告)日：2005-11-24

申请号：US11126302

申请日：2005-05-11

申请人： Hidetoshi Yamanaka ,  Toshiyuki Nishihara ,  Shigeru Atsumi ,  Daisuke Yoshioka

发明人： Hidetoshi Yamanaka ,  Toshiyuki Nishihara ,  Shigeru Atsumi ,  Daisuke Yoshioka

IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C11/18 ,  G11C16/04 ,  G11C16/26 ,  G11C5/00

CPC分类号： G11C7/1039 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C8/06 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/107

摘要： A semiconductor memory device able to read out data at a high speed continuously, provided with, corresponding to a plurality of banks, current address registers for holding addresses for reading data of cell arrays, reserved address registers able to receive in advance and hold reserved addresses for next read operations from the outside, and bank control circuits for making the current address registers hold reserved addresses held in the reserved address registers, making the data be read out, and making the data latch circuits hold the data when the data read out from the cell arrays of the banks by addresses held in the current address registers and held in the data latch circuits become able to be transferred to the outside, and a signal processing system relating to the same.

摘要翻译： 一种半导体存储装置，其能够连续地高速读出数据，与多个存储体相对应地设置有用于保存用于读取单元阵列的数据的地址的当前地址寄存器，能够提前接收并保持预留地址的预留地址寄存器 以及用于使当前地址寄存器保持在保留地址寄存器中的保留地址的存储体控制电路，使数据被读出，使数据锁存电路在数据从 通过保存在当前地址中并保存在数据锁存电路中的存储在存储器中的存储体的单元阵列变得能够被传送到外部，以及与其相关的信号处理系统。

公开(公告)号：US06956759B2

公开(公告)日：2005-10-18

申请号：US10416662

申请日：2002-09-24

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a bit line BL, a transistor for selection TR, a memory unit MU composed of memory cells MCM that are M in number (M≧2), and plate lines PLM that are M in number, in which each memory cell comprises a first electrode 21, a ferroelectric layer 22 and a second electrode 23; in the memory unit MU, the first electrodes 21 of the memory cells MCM are in common, and said common first electrode 21 is connected to the bit line BL through the transistor for selection TR; in the memory unit MU, the second electrode 23 of the m-th-place memory cell is connected to the m-th-place plate line PLm; and said ferroelectric-type nonvolatile semiconductor memory further comprises a circuit TRS for short-circuiting the plate lines PLM that are M in number and the common first electrode 21.

摘要翻译： 一种铁电型非易失性半导体存储器，包括位线BL，用于选择TR的晶体管，由M（= M）= M的存储单元MC M组成的存储器单元MU，以及板 其中每个存储单元包括第一电极21，铁电层22和第二电极23，其中M是数字M， 在存储单元MU中，存储单元MC M M的第一电极21是共同的，并且所述公共第一电极21通过用于选择TR的晶体管连接到位线BL; 在存储单元MU中，第m位存储单元的第二电极23连接到第m位置板线PL＆lt; m＆gt;; 并且所述铁电型非易失性半导体存储器还包括用于短路数量为M的平板线PL M M和用于公共第一电极21的电路TR SUB S＆lt; S＆gt; S。

公开(公告)号：US06882558B2

公开(公告)日：2005-04-19

申请号：US10239388

申请日：2002-01-17

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A method of operating a ferroelectric-type nonvolatile semiconductor memory comprising a memory unit having a bit line, a transistor for selection, a sub-memory unit composed of memory cells that are M in number, plate lines that are M in number, and a sense amplifier connected to the bit line; wherein each memory cell comprises a first electrode, a ferroelectric layer and a second electrode; the first electrodes of the memory cells constituting the sub-memory unit are in common with the sub-memory unit; said common first electrode is connected to the bit line through the transistor for selection; and each second electrode is connected to each plate line; said method comprising reading out data stored in the memory cell at a designated address externally designated, latching said data in the sense amplifier, and then outputting said data latched in the sense amplifier.

摘要翻译： 一种操作铁电型非易失性半导体存储器的方法，包括具有位线的存储单元，用于选择的晶体管，由存储单元组成的子存储器单元，数量为M的板极线，以及 读出放大器连接到位线; 其中每个存储单元包括第一电极，铁电层和第二电极; 构成子存储单元的存储单元的第一电极与子存储单元相同; 所述公共第一电极通过所述晶体管连接到所述位线用于选择; 并且每个第二电极连接到每个板线; 所述方法包括以外部指定的指定地址读出存储在存储单元中的数据，将所述数据锁存在读出放大器中，然后输出锁存在读出放大器中的数据。

公开(公告)号：US5523254A

公开(公告)日：1996-06-04

申请号：US230734

申请日：1994-04-21

申请人： Hiroshi Satoh ,  Yasunori Ohokubo ,  Takeshi Matsushita ,  Toshiyuki Nishihara ,  Makoto Hashimoto

发明人： Hiroshi Satoh ,  Yasunori Ohokubo ,  Takeshi Matsushita ,  Toshiyuki Nishihara ,  Makoto Hashimoto

IPC分类号： H01L29/772 ,  H01L21/762 ,  H01L23/544 ,  H01L27/108 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L21/76251 ,  H01L27/1082 ,  H01L27/10832 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S438/975 ,  Y10S438/977

摘要： A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

摘要翻译： 一种用于形成SOI结构的晶片接合方法，包括以下步骤：使晶片在与一个晶片的状态相接近的状态下与另一个晶片略微，基本上均匀的间隙，并将两个晶片的至少一个晶片的一个点压在另一个晶片上 晶圆。 在本发明的另一方面，提供了一种使用在SOI衬底上形成的对准标记部分和/或游标部分进行光刻定位的方法，其包括以下步骤：去除对准标记部分对应的半导体层部分和/ 或游标部分。 在本发明的另一方面，提供了一种通过使用SOI结构形成的新的DRAM半导体器件，其包括沿字线纵向形成的栅格节点的新图案。 此外，提供了通过使用SOI结构形成的新的DRAM半导体器件，其包括具有导电侧壁的独特的栅栏节点。

公开(公告)号：US5424566A

公开(公告)日：1995-06-13

申请号：US180458

申请日：1994-01-12

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L27/10808

摘要： A semiconductor DRAM cell capacitor comprises an accumulation electrode (3) formed of a p-type semiconductor, and a capacitor insulating film (5) formed between the accumulation electrode (3) and the counter electrode (4). The potential of the counter electrode (4) is fixed at a ground potential. The semiconductor DRAM cell capacitor reduces the size of an associated chip and reduces the power consumption of the associated DRAM.

摘要翻译： 半导体DRAM单元电容器包括由p型半导体形成的累积电极（3）和形成在累积电极（3）和对电极（4）之间的电容器绝缘膜（5）。 对置电极（4）的电位固定在接地电位。 半导体DRAM单元电容器减小相关芯片的尺寸并降低相关DRAM的功耗。

公开(公告)号：US5286673A

公开(公告)日：1994-02-15

申请号：US880401

申请日：1992-05-08

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L21/441

CPC分类号： H01L21/76816 ,  H01L21/76897 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/928 ,  Y10S438/975

摘要： A position alignment mark is formed by simultaneously forming on a silicon substrate an alignment marking contact hole and a back surface electrode contact hole, respectively, in a field zone and an element zone. A wiring pattern layer and a back surface electrode are formed on the field zone and element zone, respectively. A silicon layer is cut from the back surface of the silicon substrate to expose the wiring pattern layer and an alignment marking contact hole pattern. The contact hole pattern is then used as an alignment mark for forming a surface electrode.

摘要翻译： 在场地区域和元件区域中分别同时在硅衬底上形成对准标记接触孔和背面电极接触孔来形成位置对准标记。 分别在场区域和元件区域上形成布线图案层和背面电极。 从硅衬底的背面切割硅层，以露出布线图案层和对准标记接触孔图案。 然后将接触孔图案用作形成表面电极的对准标记。

公开(公告)号：US08456558B2

公开(公告)日：2013-06-04

申请号：US12829807

申请日：2010-07-02

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H04N3/14 ,  H04N5/335 ,  H01L27/00

CPC分类号： H04N5/3745 ,  H01L27/14609 ,  H04N5/357 ,  H04N5/3742 ,  H04N5/378

摘要： A pixel circuit includes: a photoelectric conversion device; a source-follower circuit; a transfer transistor that transfers charge generated in the photoelectric conversion device to an input node of the source-follower circuit; and a readout system that reads out a signal in response to the generated charge through the source-follower circuit, wherein the readout system floats the input node of the source-follower circuit and turns on the transfer transistor to transfer the signal charge to the input node, includes a function of turning off the transfer transistor, sensing an output node potential of the source-follower circuit, and reading out an output signal, and further includes an output modulation degree control function unit that temporarily reduces an output modulation degree of the source-follower circuit when the transfer transistor is turned on.

摘要翻译： 像素电路包括：光电转换装置; 源跟踪器电路; 传输晶体管，其将在所述光电转换装置中产生的电荷传送到所述源极跟随器电路的输入节点; 以及读出系统，其响应于通过源极跟随器电路产生的电荷而读出信号，其中读出系统漂移源极跟随器电路的输入节点并接通传输晶体管以将信号电荷传送到输入 节点，包括关闭转移晶体管的功能，感测源极跟随器电路的输出节点电位，以及读出输出信号，并且还包括输出调制度控制功能单元，其暂时降低输出调制度的输出调制度 源极跟随器电路，当传输晶体管导通时。

公开(公告)号：US08319850B2

公开(公告)日：2012-11-27

申请号：US12607194

申请日：2009-10-28

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H04N5/228 ,  H04N3/14 ,  H04N5/335

CPC分类号： H04N5/341 ,  H04N5/353 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/378

摘要： An imaging element includes: a pixel section in which a plurality of pixels each having a photoelectric conversion element are arranged in a matrix; a signal line to which a signal read from the pixels is transmitted; a holding section for holding the read signal during a holding period; a processing section for performing signal processing on the read signal after being held by the holding section; and a control section for controlling supply of the read signal to the holding section. The control section supplies the read signal to the holding section to cause it to hold the read signal during the holding period, and stops supplying the read signal to the holding section to cause the processing section to perform the signal processing on the read signal and to cause a signal to be read from the pixels and output to the signal line after the holding.

摘要翻译： 成像元件包括：像素部，其中具有光电转换元件的多个像素以矩阵形式布置; 发送从像素读取的信号的信号线; 保持部，用于在保持期间保持读取信号; 处理部分，用于在被保持部分保持之后对读取信号执行信号处理; 以及控制部分，用于控制向保持部分提供读取信号。 控制部分将读取信号提供给保持部分以使其在保持期间保持读取信号，并且停止向保持部分提供读取信号，以使处理部分对读取信号执行信号处理，并且 使得从像素读出信号并在保持之后输出到信号线。

公开(公告)号：USD624473S1

公开(公告)日：2010-09-28

申请号：US29333861

申请日：2009-03-16

申请人： Toshiyuki Nishihara

设计人： Toshiyuki Nishihara