公开(公告)号：US20050127944A1

公开(公告)日：2005-06-16

申请号：US11050111

申请日：2005-02-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US06895570B2

公开(公告)日：2005-05-17

申请号：US10057232

申请日：2002-01-25

申请人： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

发明人： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/177

CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077

摘要： An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.

摘要翻译： 本发明的实施例涉及将可编程逻辑器件（“PLD”）内的多个功能块互连的导线。 确定电线最佳物理长度。 具有最佳物理长度的导线尽可能快地将信号沿导线传送。 在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。 如本文所使用的物理长度是测量的线的长度。 如本文所使用的，线的逻辑长度是导线跨越的功能块的数量。 假设功能块具有不同的高度和宽度，则线的逻辑长度根据线的方向而变化。 路由架构是包括功能块的行和列的数组。 数组的列与水平线（“H-line”）连接，阵列与垂直线（“V线”）连接，H线的类型包括四条功能块的H4线 ，一个跨越八个功能块的H8线，以及跨越二十四个功能块的H24线，V线的类型包括跨越四个功能块的V4线，跨越八个功能块的V8线，以及V16线 线跨越十六个功能块。

公开(公告)号：US06630842B1

公开(公告)日：2003-10-07

申请号：US10140287

申请日：2002-05-06

申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

IPC分类号： H03K19177

CPC分类号： H03K19/17736

摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

公开(公告)号：US06590419B1

公开(公告)日：2003-07-08

申请号：US09478097

申请日：1999-10-12

申请人： Vaughn Betz ,  Jonathan Rose

发明人： Vaughn Betz ,  Jonathan Rose

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

摘要翻译： 提出了一种用于可编程逻辑器件（PLD）的互连结构，其中异构互连资源可以根据两个或多个操作参数（例如信号传播速度，电路面积，信号路由灵活性）可编程地连接到功能块， 和PLD可靠性。 可编程互连资源包括不平衡多路复用器，不同类型的接口缓冲器和不同宽度和不同线对线间距的信号线。

公开(公告)号：US5537341A

公开(公告)日：1996-07-16

申请号：US387402

申请日：1995-02-10

申请人： Jonathan Rose ,  Vaughn Betz

发明人： Jonathan Rose ,  Vaughn Betz

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5054

摘要： The use of more than one field-programmable gate array design with a given logic capacity produces advantages over the use of a single field-programmable gate array design. The designs of the field-programmable gate arrays in the family are be selected so that each field-programmable gate array design advantageously implements a different type of circuit. This use can select from the family of FPGAs with the same logic capacity such that the circuits can on average be implemented faster and/or in a smaller area.

摘要翻译： 使用具有给定逻辑容量的多个现场可编程门阵列设计产生优于使用单个现场可编程门阵列设计的优点。 可以选择族中的现场可编程门阵列的设计，使得每个现场可编程门阵列设计有利地实现不同类型的电路。 这种使用可以从具有相同逻辑容量的FPGA系列中进行选择，使得电路平均可以更快地实现和/或在较小的区域中实现。

公开(公告)号：US11018668B2

公开(公告)日：2021-05-25

申请号：US16190987

申请日：2018-11-14

申请人： Shuze Zhao ,  Olivier Trescases ,  Ibrahim Ahmed ,  Vaughn Betz ,  THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO

发明人： Shuze Zhao ,  Olivier Trescases ,  Ibrahim Ahmed ,  Vaughn Betz

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03M7/16 ,  H03M1/12 ,  H03M1/50

摘要： Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

公开(公告)号：US08732639B1

公开(公告)日：2014-05-20

申请号：US12384377

申请日：2009-04-03

申请人： Ryan Fung ,  Vaughn Betz ,  David Neto

发明人： Ryan Fung ,  Vaughn Betz ,  David Neto

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/84

摘要： A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.

摘要翻译： 一种使用电子设计自动化（EDA）工具在目标设备上设计系统的方法，包括使用定时关系在系统设计中识别同步器链。 根据本发明的一个实施例，该方法包括方便地报告考虑同步的系统可靠性，并且自动保护和优化同步器链以提高系统的鲁棒性。

公开(公告)号：US08732635B2

公开(公告)日：2014-05-20

申请号：US12165665

申请日：2008-07-01

申请人： David Lewis ,  Christopher F. Lane ,  Sarathy Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy L. Lee

发明人： David Lewis ,  Christopher F. Lane ,  Sarathy Sribhashyam ,  Srinivas Perisetty ,  Tim Vanderhoek ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy L. Lee

IPC分类号： G06F17/50 ,  G06F9/455 ,  H03K3/01 ,  G05F1/10

CPC分类号： G06F17/5081 ,  G06F17/5077 ,  H03K19/17784

摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

摘要翻译： 可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。 控制电路耦合到非易失性存储器和配置存储器。 一组电压从控制电路的输出导出，并被应用于PLD内的电路。

公开(公告)号：US08671377B2

公开(公告)日：2014-03-11

申请号：US13040255

申请日：2011-03-03

申请人： David Samuel Goldman ,  Mark Bourgeault ,  Vaughn Betz ,  Alan Louis Herrmann

发明人： David Samuel Goldman ,  Mark Bourgeault ,  Vaughn Betz ,  Alan Louis Herrmann

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/72

摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

摘要翻译： 用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。 其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。 还公开了其他实施例。

公开(公告)号：US20130007689A1

公开(公告)日：2013-01-03

申请号：US13615563

申请日：2012-09-13

申请人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

发明人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

摘要翻译： 一种用于设计要在目标设备上实现的系统的方法包括在系统中为网络生成目标设备上的边界框，其中边界框标识可用于路由其相应网络的路由资源。 系统中的网络被分配给要路由的多个线程。 执行线程使得多个网络在其对应的边界框内并行路由。