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    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    71.
    发明申请
    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE 有权
    相位变化记忆体与调制结构

    公开(公告)号：US20140346425A1

    公开(公告)日：2014-11-27

    申请号：US14458804

    申请日：2014-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Michael P. Violette

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 这样的方法可以包括形成第一电极，第二电极和直接接触第一和第二电极的存储元件。 存储元件的形成可以包括通过存储元件的第一部分形成与第一电极隔离的存储元件的可编程部分，并通过存储元件的第二部分与第二电极隔离。 描述其他实施例。

    Floating body field-effect transistors, and methods of forming floating body field-effect transistors
    72.
    发明授权
    Floating body field-effect transistors, and methods of forming floating body field-effect transistors 有权
    浮体场效应晶体管，以及形成浮体场效应晶体管的方法

    公开(公告)号：US08716075B2

    公开(公告)日：2014-05-06

    申请号：US13761587

    申请日：2013-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

    Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

    MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME
    73.
    发明申请
    MEMORY ELEMENTS USING SELF-ALIGNED PHASE CHANGE MATERIAL LAYERS AND METHODS OF MANUFACTURING SAME 有权
    使用自对准相变材料层的记忆元件及其制造方法

    公开(公告)号：US20140117300A1

    公开(公告)日：2014-05-01

    申请号：US14149045

    申请日：2014-01-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu

    IPC: H01L45/00

    CPC classification number: H01L45/1691 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1675

    Abstract: A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating material element is positioned over and in contact with the first electrode. A phase change material is positioned over the first electrode and in contact with sidewalls of the insulating material element. The phase change material has a first surface in contact with a surface of the first electrode and a surface of the first dielectric material. A second electrode is in contact with a second surface of the phase change material, which is opposite to the first surface.

    Abstract translation: 记忆元件及其形成方法。 存储元件包括在第一电介质材料中的通孔内的第一电极。 绝缘材料元件位于第一电极之上并与第一电极接触。 相变材料位于第一电极上并与绝缘材料元件的侧壁接触。 相变材料具有与第一电极的表面和第一电介质材料的表面接触的第一表面。 第二电极与相变材料的与第一表面相对的第二表面接触。

    Memory elements using self-aligned phase change material layers and methods of manufacturing same
    74.
    发明授权
    Memory elements using self-aligned phase change material layers and methods of manufacturing same 有权
    使用自对准相变材料层的存储元件及其制造方法

    公开(公告)号：US08674334B2

    公开(公告)日：2014-03-18

    申请号：US13889777

    申请日：2013-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L29/04

    CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

    Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.

    Abstract translation: 记忆元件及其形成方法。 存储元件包括支撑第一电极的基板，在第一电极上的电介质层，具有暴露第一电极的一部分的通孔，形成在通孔的侧壁上并与第一电极的暴露部分接触的相变材料层， 形成在相变材料层上的绝缘材料和形成在绝缘材料上并与相变材料层接触的第二电极。

    Phase change memory adaptive programming
    75.
    发明授权
    Phase change memory adaptive programming 有权
    相变存储器自适应编程

    公开(公告)号：US08644052B2

    公开(公告)日：2014-02-04

    申请号：US13932942

    申请日：2013-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C11/00

    CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

    Abstract: Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated.

    Abstract translation: 一些实施例包括具有模块的方法和装置，其被配置为使用信号对存储器单元进行编程以使存储器单元具有编程的电阻值，以便如果编程的电阻值在目标电阻值之外，则调整该信号的编程参数值 并且如果编程的电阻值在目标电阻值范围之外，则重复编程和调整中的至少一个，该信号在每次重复编程时包括不同的编程参数值。

    STT-MRAM CELL STRUCTURES
    76.
    发明申请
    STT-MRAM CELL STRUCTURES 有权
    STT-MRAM细胞结构

    公开(公告)号：US20140024141A1

    公开(公告)日：2014-01-23

    申请号：US14037064

    申请日：2013-09-25

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L29/66

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

    Abstract translation: 提供包括非磁性桥的磁性单元结构以及制造该结构的方法。 磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。 非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

    "> BIPOLAR SWITCHING MEMORY CELL WITH BUILT-IN
    78.
    发明申请
    BIPOLAR SWITCHING MEMORY CELL WITH BUILT-IN "ON" STATE RECTIFYING CURRENT-VOLTAGE CHARACTERISTICS 有权
    具有内置“ON”状态的双极开关存储单元整流电流特性

    公开(公告)号：US20130286712A1

    公开(公告)日：2013-10-31

    申请号：US13930952

    申请日：2013-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: G11C13/00 ,  H01L45/00

    CPC classification number: G11C13/0002 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

    Abstract: A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed.

    Abstract translation: 公开了具有内置“on”状态整流IV特性的双极电流 - 电压（IV）电阻随机存取存储器单元的存储器阵列。 在一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成肖特基二极管的金属/固体电解质/半导体堆叠。 在另一个实施例中，双极开关电阻随机存取存储器单元可以具有当切换到“导通”状态时形成金属 - 绝缘体 - 金属器件的金属/固体电解质/隧道势垒/电极堆叠。 还公开了操作存储器阵列的方法。

    CONTACT FOR MEMORY CELL
    79.
    发明申请
    CONTACT FOR MEMORY CELL 有权
    联系内存单元

    公开(公告)号：US20130149861A1

    公开(公告)日：2013-06-13

    申请号：US13734476

    申请日：2013-01-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu

    IPC: H01L21/768

    CPC classification number: H01L45/06 ,  H01L21/76885 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

    Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

    Abstract translation: 具有由电介质台面的侧壁支撑的导电层的存储器单元和集成电路的触点，以及包含这种触点的存储单元以及形成这种结构的方法。

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