利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

195 条记录 (耗时 0.023 秒)

    Confined cell structures and methods of forming confined cell structures
    1.
    发明授权
    Confined cell structures and methods of forming confined cell structures 有权

    公开(公告)号：US11950514B2

    公开(公告)日：2024-04-02

    申请号：US17362322

    申请日：2021-06-29

    申请人： Micron Technology, Inc.

    发明人： Jun Liu ,  Gurtej Sandhu

    IPC分类号： H10N50/10 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

    CPC分类号： H10N50/10 ,  G11C11/161 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

    摘要： Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

    Cross-point memory with self-defined memory elements
    2.
    发明授权
    Cross-point memory with self-defined memory elements 有权

    公开(公告)号：US11282894B2

    公开(公告)日：2022-03-22

    申请号：US16390996

    申请日：2019-04-22

    申请人： Micron Technology, Inc.

    发明人： Jun Liu

    IPC分类号： H01L27/24 ,  H01L27/10 ,  H01L45/00

    摘要： Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least one structure among the first and second structures includes a semiconductor material. The second structures contact the first structures at contact locations. A region at each of the contact locations is configured as memory element to store information based on a resistance of the region. The structures can include nanowires. Other embodiments are described.

    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE
    3.
    发明申请
    PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE 有权

    公开(公告)号：US20210193916A1

    公开(公告)日：2021-06-24

    申请号：US17135102

    申请日：2020-12-28

    申请人： Micron Technology, Inc.

    发明人： Jun Liu ,  Michael P. Violette

    IPC分类号： H01L45/00

    摘要： Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element, Other embodiments are described.

    SEMICONDUCTOR DEVICES AND RELATED METHODS
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND RELATED METHODS 审中-公开

    公开(公告)号：US20200279999A1

    公开(公告)日：2020-09-03

    申请号：US16876693

    申请日：2020-05-18

    申请人： Micron Technology, Inc.

    发明人： Jun Liu ,  Kunal R. Parekh

    IPC分类号： H01L45/00 ,  H01L27/24 ,  H01L21/033 ,  H01L21/768 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    摘要： Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.