MANAGING ERROR COMPENSATION USING CHARGE COUPLING AND LATERAL MIGRATION SENSITIVITY

    公开(公告)号:US20250103218A1

    公开(公告)日:2025-03-27

    申请号:US18975874

    申请日:2024-12-10

    Abstract: A system comprising a memory device comprising a plurality of memory cells and a processing device, operatively coupled with the memory device, to perform operations. The processing device determines, for each memory cell of the plurality of memory cells, a respective value of a metric that reflects a sensitivity of a threshold voltage of the memory cell to a change in an adjacent memory cell. The processing device determines, for each wordline of a plurality of wordlines of the memory device, based on the determined values of the metric, a respective aggregate measure of adjacent cell dependence. The processing device categorizes the wordlines into one or more wordline groups based on comparing, for each wordline, the determined aggregate measure of adjacent cell dependence to at least one threshold dependence value.

    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE

    公开(公告)号:US20250004645A1

    公开(公告)日:2025-01-02

    申请号:US18886901

    申请日:2024-09-16

    Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

    Error correction with syndrome computation in a memory device

    公开(公告)号:US12032444B2

    公开(公告)日:2024-07-09

    申请号:US18329886

    申请日:2023-06-06

    CPC classification number: G06F11/1076 H03M13/00

    Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

    MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES

    公开(公告)号:US20230395168A1

    公开(公告)日:2023-12-07

    申请号:US17860711

    申请日:2022-07-08

    CPC classification number: G11C16/3459 G11C16/0483 G11C16/10

    Abstract: Embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (PV) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (RWB) increase. They can further include defining a target aggregate RWB increase amount based on the maximum RWB increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding PV voltage offsets sufficient to reach the target aggregate RWB increase amount. The embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding PV voltage offset during a memory cell access operation.

Patent Agency Ranking