公开(公告)号：US11829650B2

公开(公告)日：2023-11-28

申请号：US18103857

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Xiangang Luo ,  Jianmin Huang ,  Phong S. Nguyen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

公开(公告)号：US20230195381A1

公开(公告)日：2023-06-22

申请号：US17645683

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Zhengang Chen ,  Ting Luo

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/10 ,  G11C16/0483

Abstract: Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

公开(公告)号：US11599300B2

公开(公告)日：2023-03-07

申请号：US17234095

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Guang Hu ,  Ting Luo ,  Tao Liu

IPC: G06F3/06

Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.

公开(公告)号：US20220406388A1

公开(公告)日：2022-12-22

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di'Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US20220221993A1

公开(公告)日：2022-07-14

申请号：US17708735

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

公开(公告)号：US20220197517A1

公开(公告)日：2022-06-23

申请号：US17692683

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/14 ,  G11C16/34 ,  G06F1/3206

Abstract: Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).

公开(公告)号：US11314425B2

公开(公告)日：2022-04-26

申请号：US17051961

申请日：2019-05-07

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

公开(公告)号：US11275512B2

公开(公告)日：2022-03-15

申请号：US16406627

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/14 ,  G11C16/34 ,  G06F1/3206

Abstract: Systems and methods are disclosed, including rebuilding a logical-to-physical (L2P) data structure of a storage system subsequent to relocating assigned marginal group of memory cells of a memory array of the storage system, such as when resuming operation from a low-power state, including an asynchronous power loss (APL).

公开(公告)号：US11222692B2

公开(公告)日：2022-01-11

申请号：US16915537

申请日：2020-06-29

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US20210405726A1

公开(公告)日：2021-12-30

申请号：US17470506

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.