公开(公告)号：US20060154475A1

公开(公告)日：2006-07-13

申请号：US11034791

申请日：2005-01-13

申请人： Manoj Mehrotra ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Amitabh Jain

IPC分类号： H01L21/4763 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

公开(公告)号：US20050112830A1

公开(公告)日：2005-05-26

申请号：US10816776

申请日：2004-04-02

申请人： Amitabh Jain ,  Lance Robertson

发明人： Amitabh Jain ,  Lance Robertson

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/6659

摘要： The invention describes a method for forming ultra shallow junction formation. Dopant species are implanted into a semiconductor. Solid phase epitaxy anneals and subsequent ultra high temperature anneals are performed following the implantation processes.

摘要翻译： 本发明描述了形成超浅结结形成的方法。 将掺杂物质注入到半导体中。 在植入过程之后进行固相外延退火和随后的超高温退火。

公开(公告)号：US06743705B2

公开(公告)日：2004-06-01

申请号：US10287979

申请日：2002-11-05

申请人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L29/6656

摘要： A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C. The method further includes the step of fourth (50), implanting deep source/drain regions (761, 762) into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers.

摘要翻译： 一种形成包括衬底（64）的集成电路（60）装置的方法（40）。 该方法包括第一步骤（42）的步骤，与衬底形成固定关系的栅叠层（62），栅叠层包括具有侧壁的栅极。 该方法还包括第二步骤（42），将源极/漏极延伸部分（701,702）注入到衬底中并相对于栅极堆叠自对准。 该方法还包括第三（46,48）的步骤，形成与侧壁成固定关系的第一侧壁形成层（72），并形成与侧壁成固定关系的第二侧壁形成层（74）。 形成第二侧壁形成层的步骤包括在等于或大于约850℃的温度下沉积第二侧壁形成层。该方法还包括第四（50）的步骤，将深源/漏区（ 761,762）插入衬底并且相对于栅极堆叠以及第一和第二侧壁形成层自对准。

公开(公告)号：US06709938B2

公开(公告)日：2004-03-23

申请号：US10197988

申请日：2002-07-18

申请人： Donald S. Miles ,  Douglas T. Grider ,  P. R. Chidambaram ,  Amitabh Jain

发明人： Donald S. Miles ,  Douglas T. Grider ,  P. R. Chidambaram ,  Amitabh Jain

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823864

摘要： An improved source/drain extension process is provided by the following processing steps of implanting NMOS devices directly on either side of the gates without an oxide layer (step D2), covering the gates with a cap oxide layer(step E2), covering NMOS devices with photoresist(step F2), dry etching all PMOS devices (Step G2), and implanting PMOS devices (step I2).

摘要翻译： 通过以下处理步骤，通过以下处理步骤提供改进的源极/漏极扩展过程，即将NMOS器件直接注入到栅极的任一侧而不具有氧化物层（步骤D2），覆盖具有帽氧化物层的栅极（步骤E2），覆盖NMOS器件 （步骤F2），干蚀刻所有PMOS器件（步骤G2）和注入PMOS器件（步骤I2）。

公开(公告)号：US06677201B1

公开(公告)日：2004-01-13

申请号：US10261407

申请日：2002-10-01

申请人： Haowen Bu ,  Amitabh Jain

发明人： Haowen Bu ,  Amitabh Jain

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/3145 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed using BTBAS processes.

摘要翻译： 在MOS晶体管制造工艺中在侧壁形成工艺期间使用CVD氮氧化物和BTBAS氮化物的方法。 氧氮化硅层（110）和氮化硅层（120）用于形成MOS晶体管的侧壁。 使用BTBAS工艺形成氮化硅层（120）。

公开(公告)号：US06482688B2

公开(公告)日：2002-11-19

申请号：US09822998

申请日：2001-03-30

申请人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

发明人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

IPC分类号： H01L21338

CPC分类号： H01L21/28114 ,  H01L21/28123

摘要： A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

摘要翻译： 形成大致T形结构的方法。 该方法包括形成多晶硅层堆叠，其包括多晶硅层和覆盖多晶硅层的大致非晶硅层。 该方法还包括选择性地蚀刻多晶硅/非晶硅层堆叠，其中在与其相关的过蚀刻步骤中与一般非晶硅层相关联的蚀刻速率小于与多晶硅层相关的蚀刻速率，从而导致 通常非晶硅层延伸超过多晶硅层的对应横向部分。

公开(公告)号：US08691644B2

公开(公告)日：2014-04-08

申请号：US13541957

申请日：2012-07-05

申请人： Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

发明人： Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

摘要翻译： 形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。 此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。 不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

公开(公告)号：US20130009251A1

公开(公告)日：2013-01-10

申请号：US13484592

申请日：2012-05-31

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/66 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

摘要翻译： 集成电路制造的过程包括在栅极叠层上提供（32,33）间隔物，以在沟道区域上提供水平偏移，用于在半导体中另外存储（35）一个PLDD注入剂量的直接应用（34） 密封物质以垂直地提供屏幕厚度，从而增加栅极堆叠上的间隔物，以提供与栅极堆叠水平的增加的偏移，并形成没有蚀刻的水平屏幕，并且随后提供（36）用于NLDD形成的NLDD注入剂量。 还公开了各种集成电路结构，装置和其它制造工艺以及测试过程。

公开(公告)号：US08253205B2

公开(公告)日：2012-08-28

申请号：US13016393

申请日：2011-01-28

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/70

CPC分类号： H01L21/26506 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/7848

摘要： An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).

摘要翻译： 集成电路（IC）包括多个压缩应变PMOS晶体管。 IC包括具有半导体表面的衬底。 栅堆叠形成在半导体表面中或半导体表面上，并且在栅极电介质上包括栅电极，其中沟道区位于栅电介质下方的半导体表面中。 源极和漏极区域是栅极堆叠的相对侧。 包括至少一种选自Ge，Sn和Pb的物质的至少一个压缩应变诱导区域位于PMOS晶体管的源极和漏极区域的至少一部分中，其中应变诱导区域提供1010个位错线/ cm 2 以及压缩应变诱导物质的活性浓度高于在压缩应变诱导区域中的压缩应变诱导物质的固溶度极限。 用于形成压缩应变PMOS晶体管的方法包括：在植入温度期间，使用至少一种压应变诱导物质，以剂量≥1×1015cm-2，在栅极堆叠的至少相对侧上注入; 在温度范围内注入; 273K，其中注入条件足以形成非晶区域。 使用包括1050℃至1400℃的峰退火温度和在峰值温度为＆lt; lE; 10秒的退火时间的退火条件对晶片进行退火，其中非晶区域通过固相外延（SPE）重结晶。

公开(公告)号：US08216945B2

公开(公告)日：2012-07-10

申请号：US12757665

申请日：2010-04-09

申请人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

发明人： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

IPC分类号： H01L21/311 ,  H01L21/469 ,  H01L21/31

CPC分类号： H01L22/20 ,  G03F7/70616 ,  G03F7/70783 ,  G03F7/70875 ,  H01L22/12

摘要： A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.

摘要翻译： 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。