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    High Capacity Low Cost Multi-State Magnetic Memory
    72.
    发明申请
    High Capacity Low Cost Multi-State Magnetic Memory 审中-公开
    大容量低成本多态磁存储器

    公开(公告)号：US20080246104A1

    公开(公告)日：2008-10-09

    申请号：US11866830

    申请日：2007-10-03

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82

    CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: One embodiment of the present invention includes multi-state current-switching magnetic memory element including a stack of two or more magnetic tunneling junctions (MTJs), each MTJ having a free layer and being separated from other MTJs in the stack by a seeding layer formed upon an isolation layer, the stack for storing more than one bit of information, wherein different levels of current applied to the memory element causes switching to different states.

    Abstract translation: 本发明的一个实施例包括多状态电流切换磁存储元件，其包括两个或多个磁隧道结（MTJ）的堆叠，每个MTJ具有自由层，并且通过形成的晶种层与堆叠中的其它MTJ分离 在隔离层上，用于存储多于一位的信息的堆栈，其中施加到存储器元件的不同电平的电流导致切换到不同的状态。

    Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit
    74.
    发明授权
    Internal oscillator circuit including a ring oscillator controlled by a voltage regulator circuit 有权
    内部振荡器电路包括由稳压电路控制的环形振荡器

    公开(公告)号：US6084483A

    公开(公告)日：2000-07-04

    申请号：US265192

    申请日：1999-03-10

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H03K3/03 ,  H03B5/04

    CPC classification number: H03K3/0315

    Abstract: An oscillator circuit residing internally to a semiconductor device for generating a clock signal for use by digital circuits. The oscillator circuit includes a voltage regulator circuit responsive to frequency selection signals for selecting a predetermined frequency and a supply voltage. The voltage regulator circuit is operative to generate a voltage reference signal having a voltage level being adjusted to compensate for variations due to temperature, process and supply voltage variations. The oscillator circuit further includes a ring oscillator circuit responsive to the voltage reference signal for generating a clock out signal having a particular frequency based upon the voltage level of the voltage reference signal. Wherein the frequency of the clock out signal remains substantially constant despite temperature, process and supply voltage variations in the semiconductor circuit.

    Abstract translation: 位于半导体器件内部的振荡器电路，用于产生由数字电路使用的时钟信号。 振荡器电路包括响应于用于选择预定频率和电源电压的频率选择信号的电压调节器电路。 电压调节器电路用于产生电压参考信号，该电压参考信号的电压电平被调整以补偿由温度，过程和电源电压变化引起的变化。 振荡器电路还包括响应于电压参考信号的环形振荡器电路，用于基于电压参考信号的电压电平产生具有特定频率的时钟输出信号。 其中，尽管半导体电路中的温度，过程和电源电压变化，时钟输出信号的频率保持基本恒定。

    Spacer flash cell process
    75.
    发明授权
    Spacer flash cell process 失效
    间隔闪存单元过程

    公开(公告)号：US5640031A

    公开(公告)日：1997-06-17

    申请号：US413349

    申请日：1995-03-30

    Applicant: Parviz Keshtbod

    Inventor： Parviz Keshtbod

    IPC: H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a metal, preferably tungsten or a tungsten alloy. The field oxide is selectively removed. A gate oxide is grown and a first polysilicon layer is formed and then etched to form spacers along the edges of the metal/second insulator structure. The first polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A second polysilicon layer is formed over the tunneling insulator.

    Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有金属，优选钨或钨合金。 有选择地去除场氧化物。 生长栅极氧化物并形成第一多晶硅层，然后蚀刻以沿着金属/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第一多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第二多晶硅层。

    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    76.
    发明申请
    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权
    多端口磁力随机存取存储器（MRAM）

    公开(公告)号：US20140192590A1

    公开(公告)日：2014-07-10

    申请号：US14204274

    申请日：2014-03-11

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

    Flash memory with nano-pillar charge trap
    77.
    发明授权
    Flash memory with nano-pillar charge trap 有权
    闪存与纳米柱电荷陷阱

    公开(公告)号：US08687418B1

    公开(公告)日：2014-04-01

    申请号：US12623369

    申请日：2009-11-20

    Applicant: Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

    IPC: G11C11/34

    CPC classification number: H01F41/303 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7881

    Abstract: An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.

    Abstract translation: 本发明的实施例包括非易失性存储单元，其包括以P基底间隔开的第一和第二N-扩散阱。 在第一和第二N-扩散阱和P-基底上形成第一隔离层。 纳米柱电荷陷阱层形成在第一隔离层上，并且包括散布在非导电区域之间的导电纳米柱。 存储单元还包括形成在纳米柱电荷陷阱层上的第二隔离层; 以及形成在第二隔离层上方和纳米柱电荷陷阱层的区域上方的至少一个字线。 纳米柱电荷陷阱层可用于在施加阈值电压时捕获电荷。 随后，可以读取电荷陷阱层以确定存储在非易失性存储单元中的任何电荷，其中电荷陷阱层中存在或不存在电荷对应于位值。

    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM)
    78.
    发明申请
    MULTI-PORT MAGNETIC RANDOM ACCESS MEMORY (MRAM) 有权

    公开(公告)号：US20140050009A1

    公开(公告)日：2014-02-20

    申请号：US13585774

    申请日：2012-08-14

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/02 ,  G11C11/21

    CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    MRAM Fabrication Method with Sidewall Cleaning
    79.
    发明申请
    MRAM Fabrication Method with Sidewall Cleaning 有权
    MRAM制造方法与侧壁清洁

    公开(公告)号：US20130267042A1

    公开(公告)日：2013-10-10

    申请号：US13443818

    申请日：2012-04-10

    Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: H01L21/02

    CPC classification number: H01L27/222 ,  H01L43/12

    Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

    Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

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