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78 条记录 (耗时 0.031 秒)

    Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses
    71.
    发明授权
    Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses 有权
    制造金属 - 氧化物 - 金属电容器及相关装置的方法

    公开(公告)号：US06373087B1

    公开(公告)日：2002-04-16

    申请号：US09652479

    申请日：2000-08-31

    申请人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

    发明人： Edward Belden Harris ,  Yifeng Winston Yan ,  Sailesh Mansinh Merchant

    IPC分类号： H01L31119

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76807

    摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.

    摘要翻译： 提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。 首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。 然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。 然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。 第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。 因此，第一导电元件包括​​电容器的第一板。 然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。 因此，第二导电元件包括​​电容器的第二板。 在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 第一导电元件优选由铜构成。 电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。 还提供了相关装置。

    Integrated circuit device having dual damascene capacitor
    72.
    发明授权
    Integrated circuit device having dual damascene capacitor 有权
    具有双重镶嵌电容器的集成电路器件

    公开(公告)号：US06320244B1

    公开(公告)日：2001-11-20

    申请号：US09388682

    申请日：1999-09-02

    申请人： Glenn B. Alers ,  Seungmoo Choi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

    发明人： Glenn B. Alers ,  Seungmoo Choi ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy

    IPC分类号： H01L2900

    CPC分类号： H01L27/1085 ,  H01L21/76807 ,  H01L28/82 ,  H01L28/90 ,  H01L28/91

    摘要： An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

    摘要翻译： 一种集成电路器件，包括其中具有开口的电介质层，以及电容器，其包括堆叠关系中位于开口的下电极，邻近下电极的电容器电介质层和与电容器电介质层相邻的上电极。 电容器具有基本平坦的上表面，其基本上与电介质层的相邻上表面部分齐平。 此外，下电极和电容器电介质层的边缘优选终止于电容器的上表面。 此外，电容器电介质可以包括高k，高质量和低泄漏电介质，并且防止电容器电介质被上下金属电极的金属减少。

    Method for making integrated circuit capacitor including anchored plugs
    74.
    发明授权
    Method for making integrated circuit capacitor including anchored plugs 有权
    制造集成电路电容器包括固定插头的方法

    公开(公告)号：US6103586A

    公开(公告)日：2000-08-15

    申请号：US364025

    申请日：1999-07-30

    申请人： Sundar Srinivasan Chetlur ,  James Theodore Clemens ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy ,  Hem M. Vaidya

    发明人： Sundar Srinivasan Chetlur ,  James Theodore Clemens ,  Sailesh Mansinh Merchant ,  Pradip Kumar Roy ,  Hem M. Vaidya

    IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/768 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L28/60 ,  H01L21/76838 ,  H01L21/76895

    摘要： A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. The electrodes and dielectric layers of the capacitor are formed so that they line the second trench.

    摘要翻译： 一种制造集成电路电容器的方法包括：在基片附近形成第一电介质层，在第一电介质层中形成第一开口，用导电材料填充第一开口以限定第一金属插塞，并在第一电介质层中形成沟槽 电介质层邻近第一金属插头。 互连线对准第一沟槽并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。 所述方法还包括在所述互连线上形成第二电介质层，在所述第二电介质层中形成第二开口，并用导电金属填充所述第二开口，以限定第二金属插塞，所述第二金属插塞具有主体部分和从所述第二介质层向下延伸的固定部分 主体部分，用于接合所述锚定凹部以锚定所述第二金属插塞。 在与第二金属插塞相邻的第二电介质层中形成第二沟槽，并且与第一沟槽对准。 由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。 电容器的电极和电介质层形成为使得它们与第二沟槽对齐。

    Silicon IC contacts using composite TiN barrier layer
    76.
    发明授权
    Silicon IC contacts using composite TiN barrier layer 失效
    硅IC接触使用复合TiN阻挡层

    公开(公告)号：US5972179A

    公开(公告)日：1999-10-26

    申请号：US941556

    申请日：1997-09-30

    申请人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

    发明人： Sailesh Chittipeddi ,  Sailesh Mansinh Merchant

    IPC分类号： H01L21/28 ,  C23C14/04 ,  C23C14/06 ,  C23C16/04 ,  C23C16/34 ,  H01L21/768 ,  C23C14/14

    CPC分类号： C23C14/046 ,  C23C14/0641 ,  C23C16/34 ,  H01L21/76843 ,  H01L21/76856

    摘要： The specification describes a composite TiN barrier layer structure formed by depositing a first TiN layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. Alternatively, uniform TiN layer morphology is obtained by depositing multiple CVD TiN layers as a series of thin strata, and passivating after each deposition step to fully crystallize each stratum thereby obtaining a uniformly crystallized barrier layer.

    摘要翻译： 该说明书描述了通过CVD沉积第一TiN层以获得良好的台阶覆盖形成的复合TiN阻挡层结构，随后是由PVD形成的第二TiN层，以获得均匀的表面形态，以便随后沉积铝合金接触层。 或者，通过将多个CVD TiN层作为一系列薄层沉积而获得均匀的TiN层形态，并且在每个沉积步骤之后钝化以使每个层完全结晶，从而获得均匀结晶的阻挡层。