公开(公告)号：US6051876A

公开(公告)日：2000-04-18

申请号：US2651

申请日：1998-01-05

申请人： Mark I. Gardner ,  Sey Ping Sun ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Sey Ping Sun ,  Daniel Kadosh

IPC分类号： H01L23/31 ,  H01L23/48

CPC分类号： H01L23/3171 ,  H01L2924/0002 ,  H01L2924/13091

摘要： The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.

摘要翻译： 公开了渐变钝化层的形成。 在一个实施例中，一种方法包括四个步骤。 在第一步骤中，提供半导体衬底上的至少一个晶体管。 在第二步骤中，在至少一个晶体管上形成至少一个金属化层。 在第三步骤中，氧化物层沉积在至少一个金属化层上。 最后，在第四步骤中，施加预定掺杂剂的离子注入以在至少一个金属化层上产生渐变钝化膜。

公开(公告)号：US6046471A

公开(公告)日：2000-04-04

申请号：US744405

申请日：1996-11-07

申请人： Mark I. Gardner ,  Fred N. Hause ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Fred N. Hause ,  Daniel Kadosh

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L31/119

CPC分类号： H01L29/66575 ,  H01L21/2652

摘要： A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.

摘要翻译： 一种浅结MOS晶体管，包括具有上部区域的半导体衬底，所述上部区域包括在沟道区域的任一侧上横向移位的第一和第二轻掺杂区域。 第一和第二轻掺杂区域延伸到半导体衬底的上表面下方的结深度。 第一和第二轻掺杂杂质分布位于半导体衬底的第一和第二源极/漏极区域内。 浅结晶体管还包括形成在半导体衬底的沟道区的上表面上的栅极电介质。 包括第一和第二侧壁的导电栅极形成在栅极电介质上。 栅极绝缘体形成为与导电栅极的第一和第二侧壁接触。 第一和第二源极/漏极结构形成在半导体衬底的上表面之上。 第一和第二源极/漏极结构在半导体衬底的第一和第二轻掺杂区域上横向移位。

公开(公告)号：US6040220A

公开(公告)日：2000-03-21

申请号：US950203

申请日：1997-10-14

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/7835

摘要： An asymmetrical transistor, and a gate conductor used in forming that transistor, are provided. The gate conductor is formed by removing upper portions of the gate conductor along an elongated axis which the gate conductor extends. The removed portions presents a partially retained region of lesser thickness than the fully retained region immediately adjacent thereto. An implant is then forwarded to the substrate adjacent and partially below the gate conductor. Only the partially retained portions allow a subset of the originally forwarded ions to pass into the substrate to form a lightly doped drain (LDD) between the channel and the drain. The partially retained region occurs only near the drain and not adjacent the source so that the LDD area is self-aligned between the edge of the conductor and a line of demarcation separating the fully retained portion and the partially retained portion. There may be numerous lines of demarcation and corresponding numerous thicknesses across the gate conductor length to provide a graded LDD area if desired.

摘要翻译： 提供了非对称晶体管和用于形成晶体管的栅极导体。 通过沿着栅极导体延伸的细长轴去除栅极导体的上部而形成栅极导体。 去除的部分呈现比其紧邻的完全保留区域更小的部分保留区域。 然后将植入物在栅极导体附近和部分下方转移到衬底。 只有部分保留的部分允许原始转移的离子的子集进入衬底，以在通道和漏极之间形成轻掺杂的漏极（LDD）。 部分保留的区域仅在漏极附近发生并且不邻近源极，使得LDD区域在导体的边缘与分离完全保持部分和部分保持部分的分界线之间自对准。 如果需要，跨栅极导体长度可以有许多分界线和对应的多个厚度以提供梯度的LDD面积。

公开(公告)号：US6030860A

公开(公告)日：2000-02-29

申请号：US993332

申请日：1997-12-19

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L21/00 ,  H01L21/8236

CPC分类号： H01L21/76895 ,  H01L21/8221 ,  H01L27/0688

摘要： A wafer includes levels elevated above the wafer substrate or base substrate which includes separated substrates suitable for circuit device element formation. In one embodiment, a first level dielectric is formed over circuit devices having elements formed in the wafer substrate. Contacts from the circuit elements may extend to the surface of the first level dielectric. A second dielectric is formed on the first level dielectric and etched to create separated openings with some openings exposing contacts. The openings are filled with substrate material, thus forming elevated substrates and local interconnects where exposed contact top surfaces are present. The substrate material is suitable for circuit device fabrication. Additional levels of elevated substrates and concurrently formed local interconnects may be subsequently fabricated.

摘要翻译： 晶片包括在晶片衬底或基底衬底上方升高的层，其包括适于电路器件元件形成的分离的衬底。 在一个实施例中，在具有在晶片衬底中形成的元件的电路器件上形成第一电平电介质。 来自电路元件的触点可以延伸到第一级电介质的表面。 在第一级电介质上形成第二电介质，并被蚀刻以产生具有露出触点的一些开口的分开的开口。 开口填充有基底材料，从而形成凸起的基底和存在暴露的接触顶表面的局部互连。 基板材料适用于电路器件制造。 可以随后制造附加水平的升高的基底和同时形成的局部互连。

公开(公告)号：US6027978A

公开(公告)日：2000-02-22

申请号：US787036

申请日：1997-01-28

申请人： Mark I. Gardner ,  Michael Duane ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Michael Duane ,  Daniel Kadosh

IPC分类号： H01L21/8234 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L29/1045 ,  H01L21/823412

摘要： A method of making an IGFET with a selectively doped channel region is disclosed. The method includes providing a semiconductor substrate with a device region, forming a gate over the device region, forming a masking layer that partially covers the gate and the device region, implanting a dopant into portions of the gate and the device region outside the gate that are not covered by the masking layer, transferring the dopant through the uncovered portion of the gate into a portion of an underlying channel region in the device region, thereby providing the channel region with a non-uniform lateral doping profile and adjusting a threshold voltage, and forming a source and a drain in the device region. The dopant can be implanted through the portion of the gate into the portion of the channel region, or alternatively, the dopant can be diffused from the portion of the gate into the portion of the channel region. In addition, the dopant can be the same conductivity type as the channel region, thereby increasing the dopant concentration of the portion of the channel region and adjusting the threshold voltage away from zero, or the dopant can be opposite conductivity type as the channel region, thereby decreasing the dopant concentration of the portion of the channel region and adjusting the threshold voltage towards zero. Preferably, the gate is polysilicon and the masking layer is photoresist. Advantageously, the invention is well-suited for adjusting the threshold voltage, and therefore the drive current, leakage current and speed, of selected IGFETs, so that the fastest IGFETs with the highest leakage currents can be placed in critical speed paths such as common lines in SRAM arrays.

摘要翻译： 公开了一种制造具有选择性掺杂沟道区域的IGFET的方法。 该方法包括提供具有器件区域的半导体衬底，在器件区域上形成栅极，形成部分地覆盖栅极和器件区域的掩模层，将掺杂剂注入到栅极外部的栅极和器件区域的部分， 不被掩蔽层覆盖，将掺杂剂通过栅极的未覆盖部分转移到器件区域中的下游沟道区域的一部分中，从而为沟道区域提供非均匀的横向掺杂分布并调整阈值电压， 以及在器件区域中形成源极和漏极。 掺杂剂可以通过栅极的一部分注入到沟道区的部分中，或者，掺杂剂可以从栅极的一部分扩散到沟道区的部分。 此外，掺杂剂可以是与沟道区相同的导电类型，从而增加沟道区的一部分的掺杂浓度，并将阈值电压调至零，或掺杂剂可以与沟道区相反的导电类型， 从而降低沟道区的部分的掺杂剂浓度并将阈值电压调至零。 优选地，栅极是多晶硅，掩模层是光致抗蚀剂。 有利地，本发明非常适合于调整所选IGFET的阈值电压，因此调节驱动电流，泄漏电流和速度，使得具有最高漏电流的最快的IGFET可被放置在诸如公用线路的临界速度路径 在SRAM阵列中。

公开(公告)号：US5985724A

公开(公告)日：1999-11-16

申请号：US937069

申请日：1997-09-24

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L29/66659 ,  H01L29/7835

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

公开(公告)号：US5952696A

公开(公告)日：1999-09-14

申请号：US792196

申请日：1997-01-30

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/823814

摘要： A semiconductor device and fabrication thereof is disclosed in which devices are formed on two devices regions of opposite conductivity types by selectively masking and implanting the same type of dopant into active regions of both device regions. The process includes masking part of the active regions in each device region and implanting a dopant into exposed active regions in both devices regions. The number of masking, implantation and other steps required in the fabrication process are reduced by the selective masking of various active regions. Non-symmetrically doped source and drain regions may be formed on the transistors among a group which lie closest to the opposite device region.

摘要翻译： 公开了一种半导体器件及其制造，其中通过选择性地掩蔽和将相同类型的掺杂剂注入到两个器件区域的有源区域中，在两个相反导电类型的器件区域上形成器件。 该过程包括掩蔽每个器件区域中的一部分有源区并将掺杂剂注入两个器件区域中的暴露的有源区。 通过对各种活性区的选择性掩蔽来减少制造过程中所需的掩模，注入和其它步骤的数量。 非对称掺杂的源极和漏极区域可以形成在最靠近相对器件区域的组中的晶体管上。

公开(公告)号：US5912188A

公开(公告)日：1999-06-15

申请号：US905686

申请日：1997-08-04

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76832 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76895

摘要： A method of forming a contact hole in an interlevel dielectric layer using dual etch stops includes the steps of providing a semiconductor substrate, forming a gate over the substrate, forming a source/drain region in the substrate, providing a source/drain contact electrically coupled to the source/drain region, forming an interlevel dielectric layer that includes first, second and third dielectric layers over the source/drain contact, forming an etch mask over the interlevel dielectric layer, applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop, thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer, applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop, thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact, and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask, thereby forming a third hole in the third dielectric layer that extends to the source/drain contact, wherein the first, second and third holes in combination provide the contact hole. In this manner, the contact hole is formed in the interlevel dielectric without any appreciable gouging of the underlying materials.

摘要翻译： 使用双蚀刻停止件在层间电介质层中形成接触孔的方法包括以下步骤：提供半导体衬底，在衬底上形成栅极，在衬底中形成源极/漏极区域，提供源/漏接触电耦合 形成层间电介质层，该层间介质层包括在源极/漏极接触之上的第一，第二和第三电介质层，在层间电介质层上形成蚀刻掩模，施加第一蚀刻，第一蚀刻对第一电介质具有高选择性 通过使用第二介电层作为蚀刻停止层，通过蚀刻掩模中的开口相对于第二介电层的层，从而在第一介电层中形成第一孔，该第一孔延伸到第二介电层而不延伸到第三介电层， 施加相对于第三介电层通过开口而对第二电介质层具有高度选择性的第二蚀刻 在蚀刻掩模中使用第三介电层作为蚀刻停止层，从而在第二介电层中形成延伸到第三介电层而不延伸到源极/漏极接触的第二孔，并施加高度选择性的第三蚀刻 相对于通过蚀刻掩模中的开口的源极/漏极接触的第三电介质层，从而在延伸到源极/漏极接触的第三电介质层中形成第三孔，其中组合的第一，第二和第三孔 提供接触孔。 以这种方式，接触孔形成在层间电介质中，而没有任何明显的底层材料的气刨。

公开(公告)号：US5898189A

公开(公告)日：1999-04-27

申请号：US905614

申请日：1997-08-04

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  H01L29/76 ,  H01L21/263 ,  H01L29/04

CPC分类号： H01L27/0922 ,  H01L21/8221 ,  H01L27/0688

摘要： A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer. The median oxide isolation layer is patterned and etched according to a localized oxide isolation mask in a configuration determined by the position of transistors in the base-level transistor formation and by the planned position of transistors, that are not yet formed, in an overlying elevated substrate level. The median oxide isolation layer is patterned and etched in a configuration so that isolation is achieved in a predetermined manner, for example, on an individual transistor basis, a transistor group basis, or the like. The resulting electronic integrated circuit structure is used for high speed circuit applications due to high packing densities and small distances between devices.

摘要翻译： 制造了多维晶体管结构，其包括形成晶体管的基极晶体管基板。 形成了一个升高的衬底，覆盖着基极晶体管，并且在升高的衬底下方的局部区域中形成氧化物隔离层，但覆盖在基极晶体管衬底上。 在衬底晶片上形成多个晶体管，以形成基极晶体管结构。 层叠电介质（ILD）层沉积在基极晶体管结构之上。 覆盖ILD层，通过第一多晶硅层的沉积，氧化物隔离层的沉积和第二多晶硅层的沉积形成“三明治”结构。 根据局部氧化物隔离掩模对中间氧化物隔离层进行构图和蚀刻，该隔离掩模的形状由基极晶体管形成中的晶体管的位置和尚未形成的晶体管的预定位置确定 底物水平。 对中间氧化物隔离层进行图案化和蚀刻，以使得以预定的方式实现隔离，例如基于单个晶体管，基于晶体管组等。 所得的电子集成电路结构由于高封装密度和器件之间的距离小而用于高速电路应用。

公开(公告)号：US5885877A

公开(公告)日：1999-03-23

申请号：US837581

申请日：1997-04-21

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Daniel Kadosh ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Daniel Kadosh ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28035 ,  H01L29/4916

摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.

摘要翻译： 复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。 下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。 第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。 通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层 ，并通过原位沉积氮掺杂的第一多晶硅层。 完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。 此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。 本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。