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公开(公告)号：US11961588B2
公开(公告)日：2024-04-16
申请号：US17590528
申请日：2022-02-01
Applicant: Micron Technology, Inc.
Inventor： Corrado Villa
CPC classification number: G11C8/16 , G11C7/04 , G11C7/1012 , G11C7/1045 , G11C8/10 , G11C2029/1804 , G11C2207/2245
Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
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公开(公告)号：US11948651B2
公开(公告)日：2024-04-02
申请号：US17903739
申请日：2022-09-06
Applicant: Micron Technology, Inc.
Inventor： Corrado Villa , Shane D. Moser
IPC: G11C29/18 , G11C11/22 , G11C11/408 , G11C11/419 , G11C13/00 , G11C16/04
CPC classification number: G11C29/18 , G11C11/2253 , G11C11/2275 , G11C11/4085 , G11C11/419 , G11C13/0028 , G11C13/003 , G11C16/0483 , G11C2029/1804
Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.
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公开(公告)号：US11651809B2
公开(公告)日：2023-05-16
申请号：US17231704
申请日：2021-04-15
Applicant: Micron Technology, inc.
Inventor： Corrado Villa , Andrea Martinelli
CPC classification number: G11C11/2259 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/221 , G11C11/2255 , G11C11/2257 , G11C11/2295
Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
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公开(公告)号：US20230031126A1
公开(公告)日：2023-02-02
申请号：US17903739
申请日：2022-09-06
Applicant: Micron Technology, Inc.
Inventor： Corrado Villa , Shane D. Moser
IPC: G11C29/18 , G11C11/419 , G11C11/408 , G11C11/22 , G11C13/00 , G11C16/04
Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.
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公开(公告)号：US20220172778A1
公开(公告)日：2022-06-02
申请号：US17108763
申请日：2020-12-01
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Jeffrey E. Koelling , Hari Giduturi , Riccardo Muzzetto , Corrado Villa
IPC: G11C13/00
Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.
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Patent Agency Ranking
公开(公告)号：US20220172750A1
公开(公告)日：2022-06-02
申请号：US17671000
申请日：2022-02-14
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Corrado Villa
Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.
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公开(公告)号：US20220091933A1
公开(公告)日：2022-03-24
申请号：US17479798
申请日：2021-09-20
Applicant: Micron Technology, Inc.
Inventor： Corrado Villa , Graziano Mirichigni , Ferdinando Bedeschi
Abstract: A memory apparatus and a method for operating the same. The method includes performing a read operation on a set of memory cells, detecting an error in data read from the set of memory cells based on an error correction code (ECC) operation performed on the data, and performing a scrubbing operation or a refreshing operation on the set of memory cells according to a detecting result.
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公开(公告)号：US20220077236A1
公开(公告)日：2022-03-10
申请号：US17497461
申请日：2021-10-08
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Paolo Tessariol
Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.
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公开(公告)号：US20210225938A1
公开(公告)日：2021-07-22
申请号：US16771658
申请日：2019-12-18
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Paolo Tessariol
Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.
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公开(公告)号：US10991411B2
公开(公告)日：2021-04-27
申请号：US16104693
申请日：2018-08-17
Applicant: Micron Technology, Inc.
Inventor： Corrado Villa , Andrea Martinelli
Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation, such as an equalization operation or a dissipation operation, based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. Selecting one of the memory sections for a voltage adjustment operation may also be based on a timer. Equalizing a bias may include biasing a plate line, which may be coupled to a ferroelectric capacitor of a memory cell, to a ground voltage or some non-zero voltage. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
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