公开(公告)号：US20170110198A1

公开(公告)日：2017-04-20

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US09466380B2

公开(公告)日：2016-10-11

申请号：US13957377

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada ,  Tomoharu Tanaka

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

公开(公告)号：US09443610B1

公开(公告)日：2016-09-13

申请号：US14730372

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Shigekazu Yamada ,  Allahyar Vahidimowlavi ,  Jae-Kwan Park ,  Cairong Hu ,  Kalyan Kavalipurapu

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G01R31/02

CPC classification number: G11C29/025 ,  G01R31/025 ,  G11C16/0483 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.

Abstract translation: 系统包括第一开关，放大器，第二开关和电容器。 第一开关电耦合在第一参考电压和节点之间。 放大器具有第一输入端，第二输入端和输出端，放大器用于在第一输入端接收第二参考电压，并在第二输入端接收采样电压。 第二开关电耦合在放大器的输出端和放大器的第二输入端之间。 电容器电耦合在放大器的第二输入端和节点之间。 关闭第一开关和第二开关以将节点初始化为第一参考电压并以单位增益配置初始化放大器。 打开第一开关和第二开关，通过感测样品电压的变化来检测泄漏电流。

公开(公告)号：US09269410B2

公开(公告)日：2016-02-23

申请号：US14584584

申请日：2014-12-29

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada

IPC: G11C7/06 ,  G11C29/02 ,  G11C29/50 ,  G11C16/00 ,  G11C16/04 ,  G11C29/12

CPC classification number: G11C7/06 ,  G11C16/00 ,  G11C16/0483 ,  G11C29/025 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.

公开(公告)号：US20140003151A1

公开(公告)日：2014-01-02

申请号：US14018926

申请日：2013-09-05

Applicant: Micron Technology, Inc.

Inventor： Shigekazu Yamada ,  Aaron Yip

IPC: G11C16/10

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

Abstract translation: 公开了用于编程选择门，存储器件和存储器系统的方法。 在一种用于编程的方法中，程序禁止电压从源传输到未选位线。 在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。 在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。