公开(公告)号：US10283520B2

公开(公告)日：2019-05-07

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L21/225 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11524

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US10256249B2

公开(公告)日：2019-04-09

申请号：US15651719

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US10229923B2

公开(公告)日：2019-03-12

申请号：US15818338

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180323212A1

公开(公告)日：2018-11-08

申请号：US16031919

申请日：2018-07-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7926

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10083981B2

公开(公告)日：2018-09-25

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180261612A1

公开(公告)日：2018-09-13

申请号：US15975907

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock

IPC: H01L27/11551 ,  H01L49/02 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11578 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11582

CPC classification number: H01L27/11551 ,  G11C5/025 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/00

Abstract: Integrated circuitry comprises an array circuitry region comprising a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.

公开(公告)号：US20180219020A1

公开(公告)日：2018-08-02

申请号：US15419813

申请日：2017-01-30

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20180076209A1

公开(公告)日：2018-03-15

申请号：US15818338

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180019255A1

公开(公告)日：2018-01-18

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L23/532 ,  H01L23/528 ,  H01L21/225

CPC classification number: H01L27/11582 ,  H01L21/225 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7883

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US20170206964A1

公开(公告)日：2017-07-20

申请号：US14995709

申请日：2016-01-14

Applicant: Micron Technology, Inc.

Inventor： David Daycock

IPC: G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11551 ,  G11C5/025 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L28/00

Abstract: Integrated circuitry comprises an array circuitry region comprising a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.