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    Methods and apparatus for detecting and decoding adaptive equalization training frames
    71.
    发明授权
    Methods and apparatus for detecting and decoding adaptive equalization training frames 有权
    用于检测和解码自适应均衡训练帧的方法和装置

    公开(公告)号：US08428195B2

    公开(公告)日：2013-04-23

    申请号：US11967463

    申请日：2007-12-31

    申请人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

    发明人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

    IPC分类号： H04L27/06

    CPC分类号： H04L27/01 ,  H04L7/0066 ,  H04L7/0083 ,  H04L25/4904

    摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

    摘要翻译： 提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。 通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。 使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

    Parallel trimming method and apparatus for a voltage controlled delay loop
    72.
    发明授权
    Parallel trimming method and apparatus for a voltage controlled delay loop 有权
    用于电压控制延迟回路的平行修整方法和装置

    公开(公告)号：US07495494B2

    公开(公告)日：2009-02-24

    申请号：US11141703

    申请日：2005-05-31

    申请人： Ronald L. Freyman ,  Mohammad S. Mobin ,  Vladimir Sindalovsky ,  Lane A. Smith

    发明人： Ronald L. Freyman ,  Mohammad S. Mobin ,  Vladimir Sindalovsky ,  Lane A. Smith

    IPC分类号： H03H11/26

    CPC分类号： H03L7/0814 ,  H04L7/0337

    摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.

    摘要翻译： 提供了一种用于电压控制延迟环路的并行修整方法和装置。 电压控制延迟环中的多个延迟单元被修整。 每个延迟单元包括延迟元件和锁存缓冲器。 参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。 然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

    Serdes auto calibration and load balancing
    74.
    发明授权
    Serdes auto calibration and load balancing 有权
    Serdes自动校准和负载平衡

    公开(公告)号：US07570708B2

    公开(公告)日：2009-08-04

    申请号：US11046669

    申请日：2005-01-31

    申请人： Donald Laturell ,  Gregory Sheets ,  Lane Smith ,  Mohammad S. Mobin

    发明人： Donald Laturell ,  Gregory Sheets ,  Lane Smith ,  Mohammad S. Mobin

    IPC分类号： H04K1/02

    CPC分类号： H04L1/205

    摘要： The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.

    摘要翻译： 本发明用于通过利用在接收信号的眼图中提供的信息来自动校准SERDES设备。 特别地，本发明减轻了确定性抖动的组成部分，例如ISI和频率失真。 为了实现这个目标，本发明使得SERDES的接收端能够使用成本函数评估所接收的眼睛的质量。 本发明计算与接收到的数据相关联的成本函数，然后使用该信息来实现SERDES设备的自动校准。

    Method and apparatus for adaptive determination of timing signals on a high speed parallel bus
    75.
    发明授权
    Method and apparatus for adaptive determination of timing signals on a high speed parallel bus 有权
    用于在高速并行总线上自适应确定定时信号的方法和装置

    公开(公告)号：US07218557B1

    公开(公告)日：2007-05-15

    申请号：US11318952

    申请日：2005-12-23

    申请人： James D. Chlipala ,  Mohammad S. Mobin

    发明人： James D. Chlipala ,  Mohammad S. Mobin

    IPC分类号： G11C8/18

    CPC分类号： G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： Methods and apparatus are provided for adaptive determination of timing signals, such as on a high speed parallel bus. The invention adaptively determines a timing signal having a first edge with respect to an internal clock, wherein the timing signal includes a period in which the timing signal is undriven, followed by a period immediately before a first transition in which the timing signal is in a predefined state. The timing signal is evaluated using one or more comparators; and an output of the one or more comparators are latched based on a clock signal. The clock signal is adjusted until the one or more comparators indicate the timing signal is in the known and valid state. The clock signal is further adjusted until the one or more comparators indicate the first transition has been reached. Thereafter, a gating control signal is established based on a timing of the first transition.

    摘要翻译： 提供了用于自适应确定定时信号的方法和装置，例如在高速并行总线上。 本发明自适应地确定具有相对于内部时钟的第一边缘的定时信号，其中定时信号包括定时信号未驱动的周期，之后紧接在其中定时信号处于 预定义状态。 使用一个或多个比较器来评估定时信号; 并且一个或多个比较器的输出基于时钟信号被锁存。 调整时钟信号直到一个或多个比较器指示定时信号处于已知和有效状态。 进一步调整时钟信号，直到一个或多个比较器指示已经达到第一转换。 此后，基于第一转换的定时建立选通控制信号。

    Communications system including lower rate parallel electronics with skew compensation and associated methods
    76.
    发明授权
    Communications system including lower rate parallel electronics with skew compensation and associated methods 有权
    通信系统包括具有偏斜补偿的低速并行电路和相关方法

    公开(公告)号：US06675327B1

    公开(公告)日：2004-01-06

    申请号：US09460165

    申请日：1999-12-13

    申请人： Mohammad S. Mobin ,  Michael S. Shaffer ,  Himanshu Mahendra Thaker ,  Charles Albert Webb, III ,  Lesley Jen-Yuan Wu

    发明人： Mohammad S. Mobin ,  Michael S. Shaffer ,  Himanshu Mahendra Thaker ,  Charles Albert Webb, III ,  Lesley Jen-Yuan Wu

    IPC分类号： G11B500

    CPC分类号： H04L1/0061 ,  H04J3/0626 ,  H04L25/4904

    摘要： A communications system includes a first device comprising a plurality of electrical-to-transmission medium converters, and a second device comprising a plurality of transmission medium-to-electrical converters to be connected to respective ones of the electrical-to-transmission medium converters via at least one transmission medium and defining parallel communications channels between the first and second devices, and wherein deskewing is provided. More particularly, the first device may include a string-based framing coder for determining and appending a string-based framing code to each information symbol string of information symbol strings to be transmitted in parallel over respective parallel communications channels. Each string-based framing code is based upon at least some of the information symbols in the respective information symbol string. The second device preferably comprises a deskewer for aligning received information symbol strings based upon the string-based framing codes. The symbols may be binary bits, and the string-based codes may be CRC codes.

    摘要翻译： 通信系统包括包括多个电传输介质转换器的第一设备和包括多个传输介质到电转换器的第二设备，所述多个传输介质到电转换器经由 至少一个传输介质并且在第一和第二设备之间定义并行通信信道，并且其中提供了去歪斜。 更具体地，第一设备可以包括基于串的成帧编码器，用于确定并将基于字符串的成帧代码附加到要在各个并行通信信道上并行发送的信息符号串的每个信息符号串。 每个基于字符串的成帧代码基于相应信息符号串中的至少一些信息符号。 第二装置优选地包括用于基于基于字符串的成帧代码来对准所接收的信息符号串的偏台。 符号可以是二进制位，并且基于字符串的代码可以是CRC码。

    Power and time saving initial tracebacks
    77.
    发明授权
    Power and time saving initial tracebacks 失效
    功率和时间节省初始回溯

    公开(公告)号：US5490178A

    公开(公告)日：1996-02-06

    申请号：US153333

    申请日：1993-11-16

    申请人： David M. Blaker ,  Gregory S. Ellard ,  Mohammad S. Mobin

    发明人： David M. Blaker ,  Gregory S. Ellard ,  Mohammad S. Mobin

    IPC分类号： H04L25/08 ,  H03M13/23 ,  H03M13/41 ,  H04L25/03 ,  H04L27/06 ,  H03M13/12

    CPC分类号： H03M13/6331 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4169 ,  H03M13/6502 ,  H03M13/6569 ,  H04L25/03178

    摘要： A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register. The second predetermined length is selected relative to the predetermined symbol instant to assure tracebacks do not cycle into branch origin data from a previous transmission burst. After all updates are complete, the update instruction is omitted and the traceback instruction repeatedly executed until all symbols from a transmission burst are decoded.

    摘要翻译： 公开了一种包括维特比解码器的数字通信系统，用于跟踪通过各种状态信息的网格和操作方法的路径。 追溯确定解码的符号。 分支原始数据的格架存储在寄存器阵列中。 与符号时刻相关联的分支原始数据是一个单元。 通过对协处理器执行数字信号处理（DSP）的更新指令来生成数据单元。 将第一预定回溯长度写入回溯长度寄存器。 第一预定回溯长度很小，以最小化从先前传输突发循环到分支原点数据的回溯。 追溯由DSP提供协处理器启动单个追溯指令。 维特比解码器在更新和追溯指令之间交替显示。 在预定的符号时刻，通过重写追溯长度寄存器来将回溯长度增加到第二预定长度。 相对于预定的符号时刻选择第二预定长度，以确保回溯不会从先前传输突发中循环到分支原点数据。 所有更新完成后，省略更新指令，并重复执行回溯指令，直到来自传输突发的所有符号被解码。

    Methods and Apparatus for Trimming of CDR Clock Buffer Using Histogram of Clock-Like Data Pattern
    78.
    发明申请
    Methods and Apparatus for Trimming of CDR Clock Buffer Using Histogram of Clock-Like Data Pattern 有权
    使用类似时钟的数据模式的直方图修剪CDR时钟缓冲器的方法和装置

    公开(公告)号：US20120173914A1

    公开(公告)日：2012-07-05

    申请号：US12982240

    申请日：2010-12-30

    申请人： Mohammad S. Mobin

    发明人： Mohammad S. Mobin

    IPC分类号： G06F1/04

    CPC分类号： H03L7/00 ,  H04L7/033 ,  H04L7/046 ,  H04L7/10

    摘要： Methods and apparatus are provided for trimming of one or more CDR clock buffers using a histogram of clock-like data patterns. One or more clock buffers in a clock and data recovery system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, wherein the first transmitted clock-like data pattern is transmitted using a first rate mode and wherein the reduced rate mode divides the first rate mode by an integer value that is greater than one; locking the clock and data recovery system using the received version of the first transmitted clock-like data pattern in the reduced rate mode; receiving a second transmitted clock-like data pattern, wherein the second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern, wherein the integer division is greater than one; and adjusting a phase of the one or more clock buffers using the second transmitted clock-like data pattern. The first and second transmitted clock-like data patterns can be transmitted by a local transmitter in a loopback mode. Generally, the received version of the first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern.

    摘要翻译： 提供了使用时钟状数据模式的直方图来修整一个或多个CDR时钟缓冲器的方法和装置。 时钟和数据恢复系统中的一个或多个时钟缓冲器通过以降低速率模式接收第一个传输的类似时钟的数据模式进行修整，其中第一个传输的类似时钟的数据模式使用第一速率模式传输，其中减少 速率模式将第一速率模式除以大于1的整数值; 使用收缩版本的第一个传输的类似时钟的数据模式以降低速率模式锁定时钟和数据恢复系统; 接收第二发送的类似时钟的数据模式，其中所述第二发送的类似时钟的数据模式具有作为所述第一发送的时钟状数据模式的游程长度的整数除法的游程长度，其中所述整数除法更大 比一个 以及使用所述第二传输的类似时钟的数据模式来调整所述一个或多个时钟缓冲器的相位。 第一和第二发送的类似时钟的数据模式可以由本地发射机以环回模式发送。 通常，第一个发送的类似时钟的数据模式的接收版本具有仅对应于第一个发送的类似时钟的数据模式的正或负边缘的边。