公开(公告)号：US20130126944A1

公开(公告)日：2013-05-23

申请号：US13303248

申请日：2011-11-23

申请人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

发明人： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC分类号： H01L29/70 ,  H01L21/331

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.

摘要翻译： 异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

公开(公告)号：US20130119436A1

公开(公告)日：2013-05-16

申请号：US13297464

申请日：2011-11-16

申请人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

发明人： Kevin K. Chan ,  Peng Cheng ,  Qizhi Liu ,  Ljubo Radic

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/73 ,  G06F17/5045 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371

摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.

公开(公告)号：US08415763B2

公开(公告)日：2013-04-09

申请号：US13076781

申请日：2011-03-31

申请人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

发明人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

IPC分类号： H01L29/66

CPC分类号： H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。 本发明包括形成半导体衬底。 接下来，在半导体衬底上形成第一掩模。 半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。 删除第一个面具。 在半导体衬底上形成第二掩模。 半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。 取下第二个掩模，并在第二个不连续的子集电极上形成集电极。 可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。 可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

公开(公告)号：US20130005108A1

公开(公告)日：2013-01-03

申请号：US13610641

申请日：2012-09-11

申请人： Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

发明人： Wade J. Hodge ,  Alvin J. Joseph ,  Rajendran Krishnasamy ,  Qizhi Liu ,  Bradley A. Orner

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L29/1004

摘要： A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

摘要翻译： 异质结双极晶体管（HBT），包括至少一个HBT的集成电路（IC）芯片和形成IC的方法。 HBT包括具有一个或多个掩埋间隙屏障层的外在基底。 外部基极可以用硼重掺杂，并且每个掩埋的间隙势垒层掺杂含有碳的掺杂剂，例如碳或SiGe：C。 外基的表面可以被硅化。

公开(公告)号：US20120248573A1

公开(公告)日：2012-10-04

申请号：US13076781

申请日：2011-03-31

申请人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

发明人： David Louis Harame ,  Alvin Jose Joseph ,  Qizhi Liu ,  Ramana Murty Malladi

IPC分类号： H01L29/70

CPC分类号： H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

摘要： Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

摘要翻译： 本发明的实施例包括形成可调谐半导体器件的方法和所得到的结构。 本发明包括形成半导体衬底。 接下来，在半导体衬底上形成第一掩模。 半导体衬底的掺杂区域不被第一掩模保护以形成第一不连续子集电极。 删除第一个面具。 在半导体衬底上形成第二掩模。 半导体衬底的掺杂区域不被第二掩模保护，并且在第一不连续子集电极的顶部上形成第二不连续子集电极。 取下第二个掩模，并在第二个不连续的子集电极上形成集电极。 可以通过改变分离第一和第二不连续子集电极内的掺杂区域的间隙来调谐器件的击穿电压。 可以以网格图案形成第一和第二不连续子集电极的掺杂区域。

公开(公告)号：US08227300B2

公开(公告)日：2012-07-24

申请号：US12632839

申请日：2009-12-08

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L21/762

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US20120126292A1

公开(公告)日：2012-05-24

申请号：US12951516

申请日：2010-11-22

申请人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

发明人： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

IPC分类号： H01L29/737 ,  G06F9/45 ,  H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

摘要翻译： 具有降低的基极电阻的异质结双极晶体管，以及用于BiCMOS集成电路的异质结双极晶体管和设计结构的制造方法。 异质结双极晶体管包括在本征基极和外部基极之间的导电层。 导电层由诸如硅化物的导电材料构成，其电阻率低于形成本征碱和非本征基的材料。

公开(公告)号：US20120112244A1

公开(公告)日：2012-05-10

申请号：US12939668

申请日：2010-11-04

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Qizhi Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/7375 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66242

摘要： Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

公开(公告)号：US07904868B2

公开(公告)日：2011-03-08

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20100237324A1

公开(公告)日：2010-09-23

申请号：US12632839

申请日：2009-12-08

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L27/12 ,  H01L21/762 ,  G06F17/50

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。