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    Semiconductor device with epitaxial source/drain facetting provided at the gate edge
    4.
    发明授权
    Semiconductor device with epitaxial source/drain facetting provided at the gate edge 有权
    具有外延源/漏极平面的半导体器件设置在栅极边缘

    公开(公告)号：US08916443B2

    公开(公告)日：2014-12-23

    申请号：US13534407

    申请日：2012-06-27

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/8238 ,  H01L27/12 ,  G06F17/50

    CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

    摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

    摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
    5.
    发明授权
    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures 有权
    具有翅片结构的半导体器件，以及形成具有翅片结构的半导体器件的方法

    公开(公告)号：US08652932B2

    公开(公告)日：2014-02-18

    申请号：US13448749

    申请日：2012-04-17

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/76

    CPC分类号： H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

    摘要翻译： 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

    Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate
    6.
    发明申请
    Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate 有权
    外延半导体电阻与半导体结构在同一基片上

    公开(公告)号：US20130307074A1

    公开(公告)日：2013-11-21

    申请号：US13472747

    申请日：2012-05-16

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/13 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/41783

    摘要： An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

    摘要翻译： 提供了一种电气装置，其包括具有上半导体层，埋入介质层和基底半导体层的衬底。 衬底中存在至少一个限定半导体器件区域和电阻器器件区域的隔离区域。 半导体器件区域包括具有存在于基极半导体层中的背栅极结构的半导体器件。 与背栅结构的电接触由穿过掩埋介电层的掺杂的外延半导体柱提供。 外延半导体电阻存在于电阻器件区域中。 从外延半导体电阻器延伸到基底半导体层的未掺杂的外延半导体柱提供了由外延半导体电阻器产生的用于散发到基极半导体层的热通路。 未掺杂和掺杂的外延半导体柱由相同的外延半导体材料组成。

    FINFET WITH ENHANCED EMBEDDED STRESSOR
    7.
    发明申请
    FINFET WITH ENHANCED EMBEDDED STRESSOR 有权
    FINFET与增强嵌入式压力机

    公开(公告)号：US20130285152A1

    公开(公告)日：2013-10-31

    申请号：US13457529

    申请日：2012-04-27

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/7851

    摘要： A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more heavily doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where at least a portion of the second semiconductor region meets the first semiconductor region.

    摘要翻译： 鳍状物FET的沟道区域具有在平行于基底表面的第一方向上具有顶点的翅片，每个翅片从顶点向下延伸，盖子覆盖顶点和相邻鳍片之间。 半导体应力区域至少沿着第一方向延伸离开翅片，以对通道区域施加应力。 鳍状物FET的源极和漏极区域可以通过沟道区域彼此分离，源极和/或漏极至少部分地在半导体应力区域中。 应力区域包括覆盖并从第一半导体区域延伸的第一半导体区域和第二半导体区域。 第二半导体区域可以比第一半导体区域更重掺杂，并且第一和第二半导体区域可以具有相反的导电类型，其中第二半导体区域的至少一部分与第一半导体区域相交。