公开(公告)号：US20150069458A1

公开(公告)日：2015-03-12

申请号：US14021795

申请日：2013-09-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming Cai ,  Bin Yang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

公开(公告)号：US08942034B2

公开(公告)日：2015-01-27

申请号：US13759344

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: G11C16/04 ,  G11C5/06 ,  G11C7/12 ,  G06F17/50 ,  G11C11/40 ,  G11C17/16 ,  G11C11/404 ,  G11C5/14

CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.

Abstract translation: 一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。 第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。 第二击穿条件是在半导体晶体管结构的覆盖区域和栅极之间。

公开(公告)号：US20140264610A1

公开(公告)日：2014-09-18

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract translation: 在详细描述中公开的实施例包括具有由伪栅极分开的连续有效区域的金属氧化物半导体（MOS）隔离方案。 MOS器件包括由具有作为n金属或p金属的功函数的材料形成的有源区域。 使用具有类似功函数的材料在该有效区域上形成活性组分。 通过在有源部件之间定位一个虚拟栅极来实现隔离。 虚拟门由相对于有源区的材料具有相反功函数的材料制成。 例如，如果有源区域是p金属材料，则虚拟栅极将由n金属制成，反之亦然。

公开(公告)号：US08836079B2

公开(公告)日：2014-09-16

申请号：US13748768

申请日：2013-01-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.

Abstract translation: 公开了具有横向移位层的金属对金属（MoM）电容器及相关系统和方法。 在一个实施例中，MoM电容器包括相对于彼此横向移位的多个垂直堆叠的层。 层的横向位移最小化累积的表面处理变化，从而形成更可靠和更均匀的电容器。

公开(公告)号：US20140203404A1

公开(公告)日：2014-07-24

申请号：US13745962

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Abstract translation: 公开了形成MoM电容器的螺旋金属金属（MoM或SMoM）电容器及相关系统和方法。 在一个实施例中，公开了一种设置在半导体管芯中的MoM电容器。 MoM电容器包括耦合到第一迹线的第一电极。 第一迹线卷绕在第一向内螺旋形的图案中并由第一平行迹线段组成。 MoM电容器还包括耦合到第二迹线的第二电极。 第二迹线卷绕在第一向内螺旋形图案中，并且包括间隔在第一平行迹线段之间的第二平行迹线段。 降低电容的变化允许电路设计者构建更严格公差的电路，并且通常提高电路的可靠性。

公开(公告)号：US20140197519A1

公开(公告)日：2014-07-17

申请号：US13743388

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/92

Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

Abstract translation: 在特定实施例中，形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露其中将形成MIM电容器的区域。 绝缘层的第二部分形成在形成在该区域内的多个沟槽表面上的第一导电层上。 该方法还包括根据剥离技术去除绝缘层的至少第三部分。

公开(公告)号：US20130320494A1

公开(公告)日：2013-12-05

申请号：US13721089

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction.

Abstract translation: 一种具有多个金属层的半导体管芯，包括一组具有最小特征尺寸的优选方向的金属层。 金属层的组合使得相邻的金属层具有彼此正交的优选方向。 形成在金属层组中的手指电容器使得形成在一个金属层中的手指电容器具有平行于该金属层的优选方向的手指方向。 在双向金属层中，电容指可以在任一方向上。

公开(公告)号：US12051534B2

公开(公告)日：2024-07-30

申请号：US17226744

申请日：2021-04-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01F27/29 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02

CPC classification number: H01F27/29 ,  H01F17/0013 ,  H01F41/041 ,  H01L28/10 ,  H01F2017/0073

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

公开(公告)号：US20240234418A9

公开(公告)日：2024-07-11

申请号：US18047954

申请日：2022-10-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.

公开(公告)号：US20240136357A1

公开(公告)日：2024-04-25

申请号：US18047954

申请日：2022-10-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Haining Yang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) comprising: a plurality of FET structures on a substrate; the plurality of FET structures comprising: a first n-type FET structure oriented in a first plane direction relative to the substrate; and a first p-type FET structure oriented in a second plane direction relative to the substrate; wherein the first n-type FET structure and the first p-type FET structure each comprises a FIN having a FIN height, H, wherein H defines the FIN height orthogonal to a surface of the substrate, each FIN being configured to transport charge carriers orthogonal to the surface of the substrate along the FIN height.