公开(公告)号：US09921909B2

公开(公告)日：2018-03-20

申请号：US14791352

申请日：2015-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： Richard Alan Stewart ,  Dexter Tamio Chun

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

公开(公告)号：US09734073B2

公开(公告)日：2017-08-15

申请号：US14929083

申请日：2015-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0804

CPC classification number: G06F12/0862 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/6026 ,  G06F2212/7203

Abstract: Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of prefetch data to be retrieved from the flash memory is determined. An access request for a flash memory is received at a cache controller in communication with a cache memory. A determination is made whether the access request for the flash memory corresponds to a portion of data stored in the cache memory. If the access request for the flash memory corresponds to the portion of data, the portion of data is returned in response to the access request. Otherwise, an N amount of prefetch data is retrieved from the flash memory and stored in the cache memory. The value N is incremented based on a cache hit percentage for the cache memory.

公开(公告)号：US09329646B2

公开(公告)日：2016-05-03

申请号：US14221171

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Victor Adrian Chiriac ,  Youmin Yu ,  Dexter Tamio Chun ,  Stephen Arthur Molloy

IPC: G06F1/20 ,  F28F21/00 ,  H05K7/20

CPC classification number: G06F1/20 ,  F28F21/00 ,  H05K7/20445

Abstract: Some implementations provide a multi-layer heat dissipating device that includes a first heat spreader layer, a first support structure, and a second heat spreader layer. The first heat spreader layer includes a first spreader surface and a second spreader surface. The first support structure includes a first support surface and a second support surface. The first support surface of the first support structure is coupled to the second spreader surface of the first heat spreader. The second heat spreader layer includes a third spreader surface and a fourth spreader surface. The third spreader surface of the second heat spreader layer is coupled to the second support surface of the first support structure. In some implementations, the first support structure is a thermally conductive adhesive layer. In some implementations, the first heat spreader layer has a first thermal conductivity, and the first support structure has a second thermal conductivity.

Abstract translation: 一些实施方案提供了一种多层散热装置，其包括第一散热器层，第一支撑结构和第二散热器层。 第一散热器层包括第一撒布机表面和第二撒布机表面。 第一支撑结构包括第一支撑表面和第二支撑表面。 第一支撑结构的第一支撑表面联接到第一散热器的第二扩张器表面。 第二散热器层包括第三扩散器表面和第四扩散器表面。 第二散热器层的第三扩散器表面联接到第一支撑结构的第二支撑表面。 在一些实施方案中，第一支撑结构是导热粘合剂层。 在一些实施方案中，第一散热器层具有第一导热性，并且第一支撑结构具有第二导热性。

公开(公告)号：US09274888B2

公开(公告)日：2016-03-01

申请号：US14081645

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Hyunsuk Shin ,  Jungwon Suh

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G06F11/14 ,  G11C29/765

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract translation: 当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。 在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到 冗余页面。

公开(公告)号：US09246716B2

公开(公告)日：2016-01-26

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Sumeet Sethi ,  John Eaton ,  Vinodh Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac Berk

IPC: H03K19/003 ,  H04L25/02 ,  H03K19/0175 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

公开(公告)号：US20150268704A1

公开(公告)日：2015-09-24

申请号：US14221171

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Victor Adrian Chiriac ,  Youmin Yu ,  Dexter Tamio Chun ,  Stephen Arthur Molloy

IPC: G06F1/20 ,  F28F21/00

CPC classification number: G06F1/20 ,  F28F21/00 ,  H05K7/20445

Abstract: Some implementations provide a multi-layer heat dissipating device that includes a first heat spreader layer, a first support structure, and a second heat spreader layer. The first heat spreader layer includes a first spreader surface and a second spreader surface. The first support structure includes a first support surface and a second support surface. The first support surface of the first support structure is coupled to the second spreader surface of the first heat spreader. The second heat spreader layer includes a third spreader surface and a fourth spreader surface. The third spreader surface of the second heat spreader layer is coupled to the second support surface of the first support structure. In some implementations, the first support structure is a thermally conductive adhesive layer. In some implementations, the first heat spreader layer has a first thermal conductivity, and the first support structure has a second thermal conductivity.

Abstract translation: 一些实施方案提供了一种多层散热装置，其包括第一散热器层，第一支撑结构和第二散热器层。 第一散热器层包括第一撒布机表面和第二撒布机表面。 第一支撑结构包括第一支撑表面和第二支撑表面。 第一支撑结构的第一支撑表面联接到第一散热器的第二扩张器表面。 第二散热器层包括第三扩散器表面和第四扩散器表面。 第二散热器层的第三扩散器表面联接到第一支撑结构的第二支撑表面。 在一些实施方案中，第一支撑结构是导热粘合剂层。 在一些实施方案中，第一散热器层具有第一导热性，并且第一支撑结构具有第二导热性。

公开(公告)号：US20150213849A1

公开(公告)日：2015-07-30

申请号：US14589145

申请日：2015-01-05

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract translation: 提供使用端口到端口环回的动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置。 在一个方面，DRAM系统中的第一端口经由环回连接耦合到第二端口。 训练信号从片上系统（SoC）发送到第一个端口，并通过环回连接传递到第二个端口。 然后训练信号返回到SoC，在那里可以通过SoC的闭环训练引擎检查训练信号。 可以记录与硬件参数对应的训练结果，并且可以重复该过程，直到在闭环训练引擎上实现硬件参数的最佳结果。 通过使用端口到端口环回配置，关于与DRAM系统相关联的定时，功率和其他参数的DRAM系统参数可以被更快地训练并且具有较低的启动存储器使用。

公开(公告)号：US20150194197A1

公开(公告)日：2015-07-09

申请号：US14591056

申请日：2015-01-07

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract translation: 公开了动态随机存取存储器（DRAM）反向通道通信系统和方法。 在一个方面，反向通道通信系统允许DRAM将错误校正信息传送到片上系统（SoC），应用处理器（AP）或其他存储器控制器上来刷新警报信息。