公开(公告)号：US20140313387A1

公开(公告)日：2014-10-23

申请号：US14355814

申请日：2012-11-08

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  Jie Shen ,  Yueyong Wang ,  Marko Aleksic

IPC: H04N5/353 ,  H04N5/3745 ,  H04N5/369

CPC classification number: H04N5/353 ,  H04N5/3355 ,  H04N5/3696 ,  H04N5/37455 ,  H04N5/37457

Abstract: In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

Abstract translation: 在集成电路图像传感器中，在连续的采样间隔之后从像素阵列中读出二进制采样值，该采样间隔共同跨越图像曝光间隔并且包括至少两个不等长度的采样间隔。 根据该像素是否产生处于第一状态或第二状态的二进制样本，阵列的每个像素在每个连续采样间隔之后有条件地重置。

公开(公告)号：US20250069641A1

公开(公告)日：2025-02-27

申请号：US18810360

申请日：2024-08-20

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Torsten Partsch ,  Wendy Elsasser

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device includes an array of storage cells. Each storage cell is coupled to one of multiple bitlines and one of multiple wordlines. A wordline decoder receives wordline address information and selectively activates an addressed wordline corresponding to the received wordline address information. The wordline decoder includes gating circuitry that is operative during a first mode of operation to selectively suppress activation of the addressed wordline during a refresh operation during a current refresh period based on a timing of an activate command associated with the addressed wordline.

公开(公告)号：US12230355B2

公开(公告)日：2025-02-18

申请号：US17634370

申请日：2020-08-13

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Liji Gopalakrishnan ,  Thomas Vogelsang

IPC: G11C7/10 ,  G11C7/22

Abstract: The memory banks of a memory device are arranged and operated in groups and the groups are further arranged and operated as clusters of these groups. Successive accesses to banks that are within different bank group clusters may be issued at a first time interval. Successive accesses to banks that are within different bank groups within the same cluster can be issued no faster than a second time interval. And, successive accesses to banks that are within the same bank group may be issued no faster than a third time interval. The memory banks of a memory device may have multiple rows open at the same time. The rows that can be open at the same time is determined by the rows that are already open. These memory banks are also arranged and operated in groups that have three different minimum time intervals.

公开(公告)号：US12223207B2

公开(公告)日：2025-02-11

申请号：US18487955

申请日：2023-10-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C29/02 ,  G11C29/04

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US12217784B2

公开(公告)日：2025-02-04

申请号：US17909940

申请日：2021-03-08

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent S. Haukness

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4094

Abstract: The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

公开(公告)号：US12001697B2

公开(公告)日：2024-06-04

申请号：US17503058

申请日：2021-10-15

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven C. Woo ,  Michael Raymond Miller

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0673

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

公开(公告)号：US11989430B2

公开(公告)日：2024-05-21

申请号：US17721176

申请日：2022-04-14

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Steven Haukness

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

公开(公告)号：US11842762B2

公开(公告)日：2023-12-12

申请号：US17439215

申请日：2020-03-16

Applicant: RAMBUS INC.

Inventor： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US20230153587A1

公开(公告)日：2023-05-18

申请号：US17910739

申请日：2021-03-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven Woo ,  Liji Gopalakrishnan

IPC: G06N3/063 ,  H10B80/00 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06N3/084 ,  H10B80/00

Abstract: A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit. The accelerator die includes a high-bandwidth memory (HBM) interface that allows a host processor to store training data and retrieve inference-model and output data from memory. The accelerator die additionally includes accelerator tiles with a direct, inter-die memory interfaces to a stack of underlying memory banks. The 3-D IC thus supports both HBM memory channels optimized for external access and accelerator-specific memory channels optimized for training and inference.

公开(公告)号：US11646090B2

公开(公告)日：2023-05-09

申请号：US17245491

申请日：2021-04-30

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/00 ,  G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

CPC classification number: G11C29/24 ,  G06F11/1008 ,  G11C29/50016 ,  G11C5/04 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.