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71.发明授权Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning 有权使用双侧壁图案形成存储器线和结构的装置和方法，用于四次半间距浮雕图案化公开(公告)号：US08679967B2
公开(公告)日：2014-03-25
申请号：US12911887
申请日：2010-10-26
IPC分类号： H01L21/4763
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译： 本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。 本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁 靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。 公开了许多附加方面。
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公开(公告)号：US08659028B2
公开(公告)日：2014-02-25
申请号：US11764789
申请日：2007-06-18
IPC分类号： H01L27/10
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
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公开(公告)号：US08649206B2
公开(公告)日：2014-02-11
申请号：US13396489
申请日：2012-02-14
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.
摘要翻译： 非易失性存储装置包括一组Y线，一组X线和与该X线组和Y线组通信的多个存储单元。 多个存储单元的每个存储单元包括静态电阻状态的电阻元件和两个或多个可逆电阻切换元件。 静态电阻状态下的电阻元件和两个以上的可逆电阻切换元件被连接到该Y线组的不同Y线。 低电阻状态下的电阻元件和两个或更多个可逆电阻切换元件连接到该X线组的公共X线。 一个或多个数据位通过在连接到特定存储单元的Y线之间引起电流而编程到多个存储单元的特定存储单元中。
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74.发明授权Continuous mesh three dimensional non-volatile storage with vertical select devices 有权连续网格三维非易失性存储与垂直选择设备公开(公告)号：US08618614B2
公开(公告)日：2013-12-31
申请号：US13323680
申请日：2011-12-12
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： H01L27/088
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译： 适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。
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75.发明授权Methods and apparatus for extending the effective thermal operating range of a memory 有权扩展存储器的有效热操作范围的方法和装置公开(公告)号：US08531904B2
公开(公告)日：2013-09-10
申请号：US13205820
申请日：2011-08-09
申请人： Tyler J. Thorp , Roy E. Scheuerlein
发明人： Tyler J. Thorp , Roy E. Scheuerlein
IPC分类号： G11C7/04
摘要： Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
摘要翻译： 提供了用于存储器集成电路（“IC”）的热调节的装置和系统。 该装置和系统可以包括存储器IC上的热传感器和耦合到热传感器的加热元件。 加热元件适于响应于来自热传感器的信号来加热存储器IC。 还提供其他方面。
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76.发明授权Memory array circuit incorporating multiple array block selection and related method 有权包含多个阵列块选择和相关方法的存储阵列电路公开(公告)号：US08509025B2
公开(公告)日：2013-08-13
申请号：US13215134
申请日：2011-08-22
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/14 , Y10T29/49002
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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77.发明授权Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography 有权在使用双镶嵌工艺和压印光刻的三维存储阵列中形成记忆线和通孔的方法和装置公开(公告)号：US08466068B2
公开(公告)日：2013-06-18
申请号：US11967638
申请日：2007-12-31
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/48 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76807 , H01L21/76817 , H01L23/5384 , H01L27/10 , H01L27/101 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.
摘要翻译： 本发明提供使用多深度压印光刻掩模和镶嵌工艺形成三维存储器阵列的系统，装置和方法。 描述了用于制造三维存储器中的存储层的压印光刻掩模。 掩模包括半透明材料，其形成有用于在用于镶嵌工艺中的转印材料中进行印记的特征，所述掩模具有多个印痕深度。 至少一个压印深度对应于用于形成存储器线的沟槽，并且至少一个深度对应于用于形成通孔的孔。 公开了许多其他方面。
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公开(公告)号：US08441849B2
公开(公告)日：2013-05-14
申请号：US13403454
申请日：2012-02-23
申请人： Tyler J. Thorp , Roy E. Scheuerlein
发明人： Tyler J. Thorp , Roy E. Scheuerlein
CPC分类号： G11C7/12 , G11C7/065 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0069
摘要： The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results.
摘要翻译： 本发明提供了调节位和字线的电压以编程两个终端存储单元的方法和装置。 本发明可以包括将连接到存储器单元的第一线路从第一线路待机电压设置为第一电压，将连接到存储器单元的第二线路从第二线路待机电压充电到预定电压，以及将第一线路从 第一电压到第二电压。 第一电压和预定电压之间的电压差使得不对存储单元进行编程的安全电压。 第二电压和预定电压之间的电压差使得可操作以编程存储器单元的编程电压结果。
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79.发明申请STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD 有权用于包含写入存储器件和写入多个存储器件的计算机的存储子系统及相关方法公开(公告)号：US20130013847A1
公开(公告)日：2013-01-10
申请号：US13616986
申请日：2012-09-14
IPC分类号： G06F12/02
CPC分类号： G06F12/0638 , G06F11/1415 , G06F12/1425 , G06F2212/2142
摘要： Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.
摘要翻译： 提供了一种计算机固态非易失性存储子系统的方法和装置。 存储子系统可以包括包括多写存储器单元的多写存储子系统存储器设备，包括一次写入存储器单元的一次写入存储子系统存储器件以及适配的基于页面的接口 读写多个存储子系统存储器件。 提供了许多其他方面。
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公开(公告)号：US08310892B2
公开(公告)日：2012-11-13
申请号：US13237773
申请日：2011-09-20
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Tianhong Yan
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Tianhong Yan
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译： 存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路 元素。 用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。
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