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公开(公告)号:US10026486B1
公开(公告)日:2018-07-17
申请号:US15451186
申请日:2017-03-06
Applicant: SanDisk Technologies LLC
Inventor: Deepanshu Dutta , Idan Alrod , Huai-Yuan Tseng , Amul Desai , Jun Wan , Ken Cheah , Sarath Puthenthermadam
Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
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公开(公告)号:US12198765B2
公开(公告)日:2025-01-14
申请号:US17750938
申请日:2022-05-23
Applicant: SanDisk Technologies LLC
Inventor: Xiang Yang , Chin-Yi Chen , Deepanshu Dutta
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.
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公开(公告)号:US12057175B2
公开(公告)日:2024-08-06
申请号:US17715647
申请日:2022-04-07
Applicant: SanDisk Technologies LLC
Inventor: Chin-Yi Chen , Muhammad Masuduzzaman , Kou Tei , Deepanshu Dutta , Hiroyuki Mizukoshi , Jiahui Yuan , Xiang Yang
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459 , G11C11/5621 , G11C11/5671
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
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公开(公告)号:US12057168B2
公开(公告)日:2024-08-06
申请号:US16899860
申请日:2020-06-12
Applicant: SanDisk Technologies LLC
Inventor: Muhammad Masuduzzaman , Deepanshu Dutta
IPC: G11C16/10 , G11C16/04 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/34 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3459 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.
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公开(公告)号:US12051467B2
公开(公告)日:2024-07-30
申请号:US16892753
申请日:2020-06-04
Applicant: SanDisk Technologies LLC
Inventor: Huai-Yuan Tseng , Henry Chin , Deepanshu Dutta
IPC: G11C16/10 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.
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公开(公告)号:US20240242764A1
公开(公告)日:2024-07-18
申请号:US18222735
申请日:2023-07-17
Applicant: SanDisk Technologies LLC
Inventor: Huiwen Xu , Deepanshu Dutta , Jia Li , Bo Lei , Ken Oowada
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08
Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.
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公开(公告)号:US11887677B2
公开(公告)日:2024-01-30
申请号:US17701365
申请日:2022-03-22
Applicant: SanDisk Technologies LLC
Inventor: Muhammad Masuduzzaman , Deepanshu Dutta , Gerrit Jan Hemink
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/10 , H10B41/27 , H10B43/27
Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.
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公开(公告)号:US11887670B2
公开(公告)日:2024-01-30
申请号:US17406224
申请日:2021-08-19
Applicant: SanDisk Technologies LLC
Inventor: Yu-Chung Lien , Deepanshu Dutta , Jiahui Yuan
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/24 , G11C16/26 , G11C16/30
Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.
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公开(公告)号:US20230410921A1
公开(公告)日:2023-12-21
申请号:US17845060
申请日:2022-06-21
Applicant: SanDisk Technologies LLC
Inventor: Xiang Yang , Deepanshu Dutta , Jiacen Guo , Takayuki Inoue , Hua-Ling Hsu
CPC classification number: G11C16/3454 , G11C16/102 , G11C16/26 , G11C7/1039
Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
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公开(公告)号:US20230377657A1
公开(公告)日:2023-11-23
申请号:US17750938
申请日:2022-05-23
Applicant: SanDisk Technologies LLC
Inventor: Xiang Yang , Chin-Yi Chen , Deepanshu Dutta
CPC classification number: G11C16/102 , G11C16/26 , G11C16/08 , G11C16/3404 , G11C16/24
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.
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