First read countermeasures in memory

    公开(公告)号:US10026486B1

    公开(公告)日:2018-07-17

    申请号:US15451186

    申请日:2017-03-06

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

    Pump skip for fast single-level cell non-volatile memory

    公开(公告)号:US12198765B2

    公开(公告)日:2025-01-14

    申请号:US17750938

    申请日:2022-05-23

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

    PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO

    公开(公告)号:US20240242764A1

    公开(公告)日:2024-07-18

    申请号:US18222735

    申请日:2023-07-17

    CPC classification number: G11C16/102 G11C16/0433 G11C16/08

    Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

    Quick pass write programming techniques in a memory device

    公开(公告)号:US11887677B2

    公开(公告)日:2024-01-30

    申请号:US17701365

    申请日:2022-03-22

    Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

    PUMP SKIP FOR FAST SINGLE-LEVEL CELL NON-VOLATILE MEMORY

    公开(公告)号:US20230377657A1

    公开(公告)日:2023-11-23

    申请号:US17750938

    申请日:2022-05-23

    CPC classification number: G11C16/102 G11C16/26 G11C16/08 G11C16/3404 G11C16/24

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

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