公开(公告)号：US20150140760A1

公开(公告)日：2015-05-21

申请号：US14597457

申请日：2015-01-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre Morin

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 可以将第一薄外延层切割并用于通过弹性弛豫向finFET的相邻沟道区施加应变。 该结构表现出优选的设计范围，用于增加应变在翅片高度上的诱导应变和均匀性。

公开(公告)号：US20140106529A1

公开(公告)日：2014-04-17

申请号：US14051174

申请日：2013-10-10

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Remi Beneyton

IPC: H01L29/66

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845

Abstract: A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.

Abstract translation: 热退火流程包括以下步骤：在硅半导体结构上沉积金属或金属合金，执行快速热退火（RTA）型的第一退火以在硅半导体结构的一部分中产生富金相， 去除未反应的金属或金属合金，并在低于硅半导体结构中存在的硅材料的熔融温度的温度下进行第二退火作为毫秒退火。

公开(公告)号：US10354927B2

公开(公告)日：2019-07-16

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20190081079A1

公开(公告)日：2019-03-14

申请号：US16180223

申请日：2018-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L29/10

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US10103174B2

公开(公告)日：2018-10-16

申请号：US14964648

申请日：2015-12-10

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

公开(公告)号：US20180144991A1

公开(公告)日：2018-05-24

申请号：US15874813

申请日：2018-01-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09917194B2

公开(公告)日：2018-03-13

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US09679899B2

公开(公告)日：2017-06-13

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09647086B2

公开(公告)日：2017-05-09

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven Bentley ,  Jody Fronheiser ,  Xin Miao ,  Joseph Washington ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

公开(公告)号：US09620626B2

公开(公告)日：2017-04-11

申请号：US14272660

申请日：2014-05-08

Applicant: Soitec ,  STMicroelectronics, Inc.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.