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公开(公告)号：US20150118805A1
公开(公告)日：2015-04-30
申请号：US14526081
申请日：2014-10-28
Inventor： Denis Rideau , Elise Baylac , Emmanuel Josse , Pierre Morin , Olivier Nier
IPC: H01L21/8234 , H01L21/324 , H01L29/78 , H01L21/265 , H01L21/84 , H01L21/762
CPC classification number: H01L21/823481 , H01L21/02356 , H01L21/02532 , H01L21/265 , H01L21/26506 , H01L21/3081 , H01L21/3105 , H01L21/31155 , H01L21/324 , H01L21/76224 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7831 , H01L29/7846 , H01L29/7847
Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠
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2.发明申请FINFET DEVICE WITH SILICIDED SOURCE-DRAIN REGIONS AND METHOD OF MAKING SAME USING A TWO STEP ANNEAL 审中-公开具有硅源排水区域的FINFET器件及使用两步法制备相同方法公开(公告)号：US20140106529A1
公开(公告)日：2014-04-17
申请号：US14051174
申请日：2013-10-10
Inventor： Pierre Morin , Remi Beneyton
IPC: H01L29/66
CPC classification number: H01L29/665 , H01L21/28518 , H01L29/41791 , H01L29/66795 , H01L29/7845
Abstract: A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (RTA) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.
Abstract translation: 热退火流程包括以下步骤：在硅半导体结构上沉积金属或金属合金，执行快速热退火（RTA）型的第一退火以在硅半导体结构的一部分中产生富金相， 去除未反应的金属或金属合金，并在低于硅半导体结构中存在的硅材料的熔融温度的温度下进行第二退火作为毫秒退火。
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公开(公告)号：US09318372B2
公开(公告)日：2016-04-19
申请号：US14526053
申请日：2014-10-28
Inventor： Olivier Nier , Denis Rideau , Pierre Morin , Emmanuel Josse
IPC: H01L21/00 , H01L21/762 , H01L29/78 , H01L27/12 , H01L21/02
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/02532 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7846 , H01L29/7847 , H01L29/7849
Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。
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公开(公告)号：US09543214B2
公开(公告)日：2017-01-10
申请号：US14526081
申请日：2014-10-28
Inventor： Denis Rideau , Elise Baylac , Emmanuel Josse , Pierre Morin , Olivier Nier
IPC: H01L21/8234 , H01L21/84 , H01L21/762 , H01L29/78 , H01L21/02 , H01L21/265 , H01L21/3115 , H01L21/308 , H01L21/3105 , H01L21/324 , H01L27/12
CPC classification number: H01L21/823481 , H01L21/02356 , H01L21/02532 , H01L21/265 , H01L21/26506 , H01L21/3081 , H01L21/3105 , H01L21/31155 , H01L21/324 , H01L21/76224 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7831 , H01L29/7846 , H01L29/7847
Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠
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公开(公告)号：US20150118823A1
公开(公告)日：2015-04-30
申请号：US14526053
申请日：2014-10-28
Inventor： Olivier Nier , Denis Rideau , Pierre Morin , Emmanuel Josse
IPC: H01L21/762 , H01L27/12 , H01L21/02 , H01L29/78
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/02532 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7846 , H01L29/7847 , H01L29/7849
Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。
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Patent Agency Ranking
公开(公告)号：US10403682B2
公开(公告)日：2019-09-03
申请号：US15968474
申请日：2018-05-01
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Pierre Morin , Philippe Brun , Laurent-Luc Chapelon
IPC: H01L27/24 , H01L45/00 , H01L23/528 , H01L23/522 , H01L23/532 , H01L21/02 , H01L21/768
Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.
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公开(公告)号：US10903423B2
公开(公告)日：2021-01-26
申请号：US16708604
申请日：2019-12-10
Inventor： Pierre Morin , Michel Haond , Paola Zuliani
Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
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公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
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公开(公告)号：US10658578B2
公开(公告)日：2020-05-19
申请号：US16168369
申请日：2018-10-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Pierre Morin , Didier Dutartre
Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.
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公开(公告)号：US10263110B2
公开(公告)日：2019-04-16
申请号：US15387712
申请日：2016-12-22
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Remy Berthelon , Didier Dutartre , Pierre Morin , Francois Andrieu , Elise Baylac
IPC: H01L29/207 , H01L27/12 , H01L21/84 , H01L21/8238 , H01L21/336 , H01L29/78 , H01L21/02 , H01L21/762 , H01L29/66
Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
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