公开(公告)号：US20240021563A1

公开(公告)日：2024-01-18

申请号：US18351748

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/27 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/48 ,  H01L24/32 ,  H01L2225/06506 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/2021

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer having a first surface on which a plurality of semiconductor chips are disposed and a second surface, opposite to the first surface. The second surface of the wafer is ground. The ground second surface of the wafer is coated with a liquid adhesive material to form an uncured adhesive layer having a thickness of 5 μm or less. The uncured adhesive layer on the wafer is semi-cured. The wafer is cut so as to separate the plurality of semiconductor chips from one another. The plurality of semiconductor chips are stacked using the semi-cured adhesive layer. The semi-cured adhesive layer disposed between the plurality of stacked semiconductor chips is fully cured.

公开(公告)号：US11810915B2

公开(公告)日：2023-11-07

申请号：US17359110

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L27/08 ,  H01L23/538 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/14 ,  H01L28/60

Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.

公开(公告)号：US11804427B2

公开(公告)日：2023-10-31

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US11694936B2

公开(公告)日：2023-07-04

申请号：US17235997

申请日：2021-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Kim ,  Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L21/683 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/16227

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

公开(公告)号：US11605584B2

公开(公告)日：2023-03-14

申请号：US17329256

申请日：2021-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20230049283A1

公开(公告)日：2023-02-16

申请号：US17730551

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyounglim SUK ,  Daewoo Kim ,  Seokhyun Lee

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package includes: hybrid-bonding a semiconductor chip, including a through-silicon via, to an upper surface of a semiconductor wafer, wet-etching a surface of the semiconductor chip to expose the through-silicon via, covering the exposed through-silicon via with a material, including an organic resin and an inorganic filler, to form an encapsulation layer, removing an upper surface of the encapsulation layer to expose the through-silicon via, and forming a redistribution structure electrically connected to the through-silicon via.

公开(公告)号：US20220302002A1

公开(公告)日：2022-09-22

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/29

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

公开(公告)号：US11145611B2

公开(公告)日：2021-10-12

申请号：US16795795

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US11075149B2

公开(公告)日：2021-07-27

申请号：US16676716

申请日：2019-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun Lee

IPC: H01L23/495 ,  H01L23/522 ,  H01L23/532

Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

公开(公告)号：US20210183766A1

公开(公告)日：2021-06-17

申请号：US17189964

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A method is proivded and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.