公开(公告)号：US20080309655A1

公开(公告)日：2008-12-18

申请号：US12195802

申请日：2008-08-21

申请人： Satoru Ito

发明人： Satoru Ito

IPC分类号： G09G5/00

CPC分类号： G11C5/147 ,  G09G3/3614 ,  G09G3/3655 ,  G11C5/145 ,  G11C29/24 ,  H02M3/07

摘要： A common voltage generation circuit includes a first operational amplifier which outputs an amplitude voltage of a common voltage based on a first power supply voltage, a second operational amplifier which outputs a high-potential-side voltage of the common voltage based on the first power supply voltage, and a low-potential-side voltage generation circuit which generates a low-potential-side voltage of the common voltage which is lower in potential than the high-potential-side voltage for the amplitude voltage by a charge-pump operation. The common voltage generation circuit supplies the high-potential-side voltage or the low-potential-side voltage to a common electrode which faces a pixel electrode specified by a scan line and a data line of an electro-optical device through an electro-optical substance.

摘要翻译： 公共电压产生电路包括基于第一电源电压输出公共电压的幅度电压的第一运算放大器，基于第一电源输出公共电压的高电位侧电压的第二运算放大器 电压和低电位侧电压产生电路，其通过电荷泵操作产生电位低于用于振幅电压的高电位侧电压的公共电压的低电位侧电压。 公共电压产生电路将高电位侧电压或低电位侧电压提供给由电光学装置的扫描线和数据线指定的像素电极的公共电极 物质。

公开(公告)号：US20070002670A1

公开(公告)日：2007-01-04

申请号：US11270549

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G11C8/00

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/3611 ,  G09G5/39 ,  G09G5/395 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2360/12

摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

摘要翻译： 一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个 位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

公开(公告)号：US20070002509A1

公开(公告)日：2007-01-04

申请号：US11477720

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： H02H9/00

CPC分类号： G09G3/3688 ,  G02F1/13452 ,  G02F2202/28 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

摘要翻译： 集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。 垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠 部分或全部静电放电保护元件ESDx。

公开(公告)号：US20070001973A1

公开(公告)日：2007-01-04

申请号：US11270632

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Katsuhiko Maki

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a logic circuit block LB, a grayscale voltage generation circuit block GB, data driver blocks DB1 to DB4, and a power supply circuit block PB. The data driver blocks DB1 to DB4 are disposed between the logic circuit block LB and the grayscale voltage generation circuit block GB, and the power supply circuit block PB.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括逻辑电路块LB，灰度电压产生电路块GB，数据驱动器块DB 1至DB 4和电源电路块PB。 数据驱动器块DB 1至DB 4设置在逻辑电路块LB和灰度级电压产生电路块GB之间，以及电源电路块PB。

公开(公告)号：US20070001969A1

公开(公告)日：2007-01-04

申请号：US11270552

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2310/027

摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, and a data read control circuit. Each of the RAM blocks is disposed along a first direction X in which the bitlines BL extend. The data read control circuit controls data reading so that data for pixels corresponding to the signal lines is read out by N times reading in one horizontal scan period 1H of the display panel (N is an integer larger than 1)

摘要翻译： 集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据。 显示存储器包括多个RAM块，每个RAM块包括多个字线WL，多个位线BL，多个存储单元MC和数据读取控制电路。 每个RAM块沿着位线BL延伸的第一方向X设置。 数据读取控制电路控制数据读取，使得对应于信号线的像素的数据在显示面板的一个水平扫描周期1H（N是大于1的整数）中读出N次读数，

公开(公告)号：US20060163638A1

公开(公告)日：2006-07-27

申请号：US11189916

申请日：2005-07-27

申请人： Satoru Ito

发明人： Satoru Ito

IPC分类号： H01L29/00 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L28/84 ,  H01L21/76816 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/10894

摘要： A semiconductor device includes a first insulating film formed on a semiconductor substrate; a second insulating film formed on the first insulating film and having a recess corresponding to a capacitor region; a lower electrode formed in the recess; a capacitor dielectric film formed on the lower electrode; and an upper electrode formed on the capacitor dielectric film. The semiconductor device further includes a conductive portion formed in the first insulating film and the second insulating film for electrically connecting the semiconductor substrate to the upper electrode.

摘要翻译： 半导体器件包括形成在半导体衬底上的第一绝缘膜; 形成在所述第一绝缘膜上并且具有与电容器区域对应的凹部的第二绝缘膜; 形成在所述凹部中的下电极; 形成在下电极上的电容器电介质膜; 以及形成在电容器电介质膜上的上电极。 半导体器件还包括形成在第一绝缘膜中的导电部分和用于将半导体衬底电连接到上电极的第二绝缘膜。

公开(公告)号：US5552639A

公开(公告)日：1996-09-03

申请号：US456384

申请日：1995-06-01

申请人： Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

发明人： Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L23/58 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34 ,  H01L29/44

CPC分类号： H01L23/585 ,  H01L23/291 ,  H01L23/3171 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

公开(公告)号：US5395915A

公开(公告)日：1995-03-07

申请号：US104920

申请日：1993-08-12

申请人： Shigeru Iimuro ,  Satoru Ito ,  Tomoko Takashima ,  Takashi Kitamura

发明人： Shigeru Iimuro ,  Satoru Ito ,  Tomoko Takashima ,  Takashi Kitamura

IPC分类号： C07C37/74 ,  C07C39/16 ,  C08G8/10 ,  C08G8/20 ,  C08G14/02 ,  C08G8/04

CPC分类号： C07C39/16 ,  C07C37/20 ,  C07C37/74 ,  C08G8/10 ,  C08G8/20 ,  Y02P20/582

摘要： Herein disclosed is a method for simultaneously preparing a highly pure bisphenol F and/or a bisphenol F for general use and a novolak phenol resin and/or a high molecular weight novolak phenol resin comprising the steps of:(1) a preparation step comprising reacting phenol with formaldehyde in the presence of an acid catalyst and removing the acid catalyst, water and the unreacted phenol from the resulting reaction product to give a crude bisphenol F;(2) a distillation step comprising distilling a part of the crude bisphenol F to give a highly pure bisphenol F, as a distillate, having a binuclear moiety-content of not less than 95% by weight and a novolak phenol resin, as a still-bottom product, having a binuclear moiety-content of not more than 15% by area;(3) a step for mixing the highly pure bisphenol F with the remaining crude bisphenol F to give a bisphenol F for general use; and(4) a step for polymerizing the novolak phenol resin with formaldehyde in the presence of an acid catalyst to give a high molecular weight novolak phenol resin.

摘要翻译： 本文公开了一种用于同时制备用于一般用途的高纯度双酚F和/或双酚F和酚醛清漆酚醛树脂和/或高分子量酚醛清漆酚树脂的方法，包括以下步骤：（1）制备步骤，包括使 苯酚与甲酸在酸催化剂存在下，从所得反应产物中除去酸催化剂，水和未反应的苯酚，得到粗双酚F; （2）蒸馏步骤，包括蒸馏粗双酚F的一部分，得到作为蒸馏物的高纯度双酚F，双核部分含量不小于95重量％，酚醛清漆酚树脂作为静止物 双产物，双核部分含量不超过面积的15％; （3）将高纯度双酚F与剩余的粗双酚F混合以得到通常使用的双酚F的步骤; 和（4）在酸催化剂存在下使酚醛清漆酚醛树脂与甲醛聚合的步骤，得到高分子量酚醛清漆酚醛树脂。

公开(公告)号：US5371411A

公开(公告)日：1994-12-06

申请号：US072405

申请日：1993-06-07

申请人： Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

发明人： Yuji Hara ,  Satoru Ito ,  Tatsuro Toya

IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L23/58 ,  H01L27/02 ,  H01L23/48 ,  H01L29/34 ,  H01L29/44

CPC分类号： H01L23/3171 ,  H01L23/291 ,  H01L23/585 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181

摘要： A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

摘要翻译： 树脂模制型半导体器件具有形成为覆盖四边形半导体衬底的表面的周缘的金属保护环。 为了防止保护环上的钝化膜由于聚集在半导体衬底的四个角中的树脂模具封装而受到应力的破坏，在保护环的角部形成有狭缝或一排小孔。

公开(公告)号：US5330796A

公开(公告)日：1994-07-19

申请号：US878461

申请日：1992-05-05

申请人： Akira Kasari ,  Satoru Ito ,  Shigeru Nakamura

发明人： Akira Kasari ,  Satoru Ito ,  Shigeru Nakamura

IPC分类号： B05D5/06 ,  B05D7/00 ,  C08L61/20 ,  C08L83/04 ,  C09D133/06 ,  C09D143/04 ,  C09D167/00 ,  B05D1/36

CPC分类号： B05D7/532 ,  B05D5/068 ,  C09D133/06 ,  C09D143/04 ,  C09D167/00 ,  B05D2451/00 ,  B05D2601/02 ,  C08L61/20 ,  C08L83/04

摘要： The invention provides a method of forming a coating film by forming in sequence a pigmented base coat and a clear top coat on a substrate followed by finishing by the two-coat one-bake technique, the method being characterized by using, as a coating composition for pigmented base coat formation, a composition comprising, as essential components thereof,(1) an OH-containing resin,(2) an amino resin,(3) a polyorganosiloxane(4) a flaky metal powder and/or a mica powder, and( 5 ) an organic solvent,and using, as a coating composition for clear top coat formation, a composition comprising, as essential components thereof,(1) an OH-containing base resin which further contains at least one group selected from the class consisting of a silanol group and a hydrolyzable group bound directly to a silicon atom,( 2 ) an amino resin, and( 3 ) an organic solvent.

摘要翻译： 本发明提供了一种形成涂膜的方法，该方法通过在基材上依次形成着色底涂层和透明面漆，然后通过双涂层单烘烤技术进行精加工，该方法的特征在于使用作为涂料组合物 用于着色底涂层形成的组合物，包含作为其主要成分的组合物，（1）含OH树脂，（2）氨基树脂，（3）聚有机硅氧烷（4）片状金属粉末和/或云母粉末， 和（5）有机溶剂，并且使用作为透明外涂层形成用涂料组合物的组合物，其包含作为其主要成分的组合物，（1）含OH基团树脂，其还含有选自以下的至少一种基团： 由硅烷醇基和直接与硅原子结合的可水解基团，（2）氨基树脂和（3）有机溶剂组成。