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120 条记录 (耗时 0.041 秒)

    Semiconductor memory device
    71.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07238988B2

    公开(公告)日：2007-07-03

    申请号：US11000045

    申请日：2004-12-01

    申请人： Kazumi Inoh ,  Takeshi Hamamoto

    发明人： Kazumi Inoh ,  Takeshi Hamamoto

    IPC分类号： H01L27/01

    CPC分类号： H01L29/7841 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.

    摘要翻译： 在半导体层中形成的扩散区域中设置硅化物膜。 硅化物膜的厚度与半导体层的厚度基本相同。 硅化物膜的底部位于绝缘膜和半导体层之间的界面附近。

    Semiconductor storage device and method of fabricating the same
    72.
    发明申请
    Semiconductor storage device and method of fabricating the same 审中-公开
    半导体存储装置及其制造方法

    公开(公告)号：US20060244076A1

    公开(公告)日：2006-11-02

    申请号：US11261537

    申请日：2005-10-31

    申请人： Takeshi Hamamoto

    发明人： Takeshi Hamamoto

    IPC分类号： H01L29/76

    CPC分类号： H01L21/26506 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/7841

    摘要： A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor regions, and element isolating regions each formed between the adjacent second conductive type semiconductor regions, a bottom surface of which being located in the first conductive type semiconductor region, wherein the number of crystal defects per unit volume in the first conductive type semiconductor region is larger than the number of the crystal defects per unit volume in the second conductive type semiconductor regions.

    摘要翻译： 一种半导体存储装置，具有形成在半导体基板上的第一导电型半导体区域，在第一导电型半导体区域上彼此分开形成的多个第二导电型半导体区域，分别形成在多个第二导电型半导体区域上的多个MOSFET 导电型半导体区域和各自形成在相邻的第二导电类型半导体区域之间的元件隔离区域，其底表面位于第一导电类型半导体区域中，其中第一导电类型半导体中的每单位体积的晶体缺陷的数量 区域大于第二导电型半导体区域中每单位体积的晶体缺陷的数量。

    Semiconductor memory device allowing accurate burn-in test
    73.
    发明授权
    Semiconductor memory device allowing accurate burn-in test 失效
    半导体存储器件允许准确的老化测试

    公开(公告)号：US07110282B2

    公开(公告)日：2006-09-19

    申请号：US10947213

    申请日：2004-09-23

    申请人： Takashi Kono ,  Takeshi Hamamoto

    发明人： Takashi Kono ,  Takeshi Hamamoto

    IPC分类号： G11C11/4063 ,  G11C11/4074 ,  G11C7/08 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  H01L29/772

    CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C29/12 ,  G11C2029/1202

    摘要： An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

    摘要翻译： 存储单元阵列中的绝缘栅型场效应晶体管是具有比阵列外围电路中的绝缘栅型场效应晶体管的栅极绝缘膜厚的栅极绝缘膜的晶体管。 可以实现DRAM（动态随机存取存储器）基于单元的半导体存储器件，其即使在低电源电压下也能够精确地执行老化测试而不降低感测操作特性。

    Semiconductor device and manufacturing method thereof
    74.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US07095081B2

    公开(公告)日：2006-08-22

    申请号：US11331316

    申请日：2006-01-13

    申请人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

    发明人： Takashi Yamada ,  Hajime Nagano ,  Takeshi Hamamoto

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

    CPC分类号： H01L21/823412 ,  H01L21/76264 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7841

    摘要： A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

    摘要翻译： 半导体器件包括具有第一至第四区域的衬底，在第一区域中的衬底上形成的第一绝缘膜，形成在第二区域中的衬底上并具有高于第一区域的上表面的上表面的第一外延层 绝缘膜，形成在所述第一绝缘膜上的第一半导体层，其具有相对于所述第一外延层设置的空间，并且具有设置在与所述第一外延层的上表面基本相同的高度的上表面;以及元件隔离绝缘膜 膜形成在该空间中，并且具有设置在与第一外延层的上表面和第一半导体层的上表面大致相同高度的上表面。

    Clock synchronous type semiconductor memory device
    78.
    发明授权
    Clock synchronous type semiconductor memory device 有权
    时钟同步型半导体存储器件

    公开(公告)号：US06757212B2

    公开(公告)日：2004-06-29

    申请号：US10034544

    申请日：2002-01-03

    申请人： Takeshi Hamamoto ,  Takeo Miki

    发明人： Takeshi Hamamoto ,  Takeo Miki

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/222

    摘要： A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

    摘要翻译： 通过利用具有取决于内部时钟信号的工作频率的延迟时间的延迟电路产生的时钟信号被施加到第一电路以激活它，以及时钟信号，其具有不依赖于 时钟频率并相对于外部时钟信号被同相调节，被施加到接收第一电路的输出信号以用于其操作的第二电路。 因此，可以将第二电路的操作定时设置为尽可能晚。 因此，可以减轻第一电路的操作条件，以实现高速数据传输。 即使在高速运行中，内部数据也可以被可靠地接收并准确传送。

    Semiconductor memory device
    79.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06597625B2

    公开(公告)日：2003-07-22

    申请号：US09976113

    申请日：2001-10-15

    申请人： Takanobu Suzuki ,  Takeshi Hamamoto

    发明人： Takanobu Suzuki ,  Takeshi Hamamoto

    IPC分类号： G11C800

    CPC分类号： G11C8/06

    摘要： A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented. Further, if the address-input buffer section 3 is divided into a plurality of address-input buffers, for example, two buffers 3a and 3b, and arranged on the memory chip 8, then the second address-latch circuit section 5 is also divided into two address-latch circuits 5a and 5b, corresponding to the address-input buffers 3a and 3b, and the address-latch circuit 5a is arranged at a neighborhood of the address-input buffer 3a, and the address-latch circuit 5b is arranged at a neighborhood of the address-input buffer 3b.

    Pattern data density inspection apparatus and density inspection method and recording medium storing pattern data density inspection program
    80.
    发明授权
    Pattern data density inspection apparatus and density inspection method and recording medium storing pattern data density inspection program 失效
    图案数据密度检查装置和密度检查方法以及存储图案数据密度检查程序的记录介质

    公开(公告)号：US06505325B1

    公开(公告)日：2003-01-07

    申请号：US09615450

    申请日：2000-07-13

    申请人： Takeshi Hamamoto

    发明人： Takeshi Hamamoto

    IPC分类号： G06F945

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A pattern density inspection apparatus is provided which improves the detection accuracy of a pattern data density error region, and outputs detection results for a designer to efficiently perform a correction operation without performing detection of pattern data density error regions which do not require correction. A control section 1 reads out layout data from a layout storage section 2, and stores this in an input processing section 3 and an output processing section 7. A data density computation processing section 4, while displacing layout data of the input processing section 3 from a position where pattern data was computed immediately before, in either one of an X axis direction and a Y axis direction, performs computations of the pattern density in the detection range after movement, and judges if the pattern data density is above 50%, and makes that above 50% a temporary error region. An error overlap removal processing section 5 takes a logical sum of temporary error regions, and creates an aggregate temporary error region. An error region width computation processing section 6 judges if an aggregate temporary error region is an error shape which contains a 400 &mgr;m square error judgment reference shape.

    摘要翻译： 提供了图案密度检查装置，其提高了图案数据密度误差区域的检测精度，并且输出检测结果以使设计者有效地执行校正操作，而不执行不需要校正的图案数据密度误差区域的检测。 控制部分1从布局存储部分2读出布局数据，并将其存储在输入处理部分3和输出处理部分7中。数据密度计算处理部分4在将输入处理部分3的布局数据从 在X轴方向和Y轴方向中的任意一个之前立即计算图案数据的位置，进行运动后的检测范围内的图案密度的计算，判断图案数据密度是否在50％以上， 使超过50％的临时错误区域。 错误重叠移除处理部分5获取临时错误区域的逻辑和，并创建聚合临时错误区域。 误差区域宽度计算处理部6判断聚合暂时错误区域是否包含400μm的平方误差判定基准形状的误差形状。