公开(公告)号：US08981562B2

公开(公告)日：2015-03-17

申请号：US12134381

申请日：2008-06-06

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

IPC分类号： H01L21/00 ,  G03F1/00 ,  G03F1/36 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

公开(公告)号：US08735235B2

公开(公告)日：2014-05-27

申请号：US12276015

申请日：2008-11-21

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Ming-Yuan Wu ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Ming-Yuan Wu ,  Mong-Song Liang

IPC分类号： H01L21/338

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833

摘要： A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

摘要翻译： 提供一种使用门最后工艺形成金属栅的方法。 在基板上形成沟槽。 沟槽的轮廓被修改以在沟槽的孔处提供第一宽度，并且在沟槽的底部提供第二宽度。 轮廓可以通过包括锥形侧壁形成。 金属栅极可以形成在具有改变的轮廓的沟槽中。 还提供了一种半导体器件，其包括在栅极顶部具有比栅极的底部更大的宽度的栅极结构。

公开(公告)号：US08624295B2

公开(公告)日：2014-01-07

申请号：US12052389

申请日：2008-03-20

申请人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

摘要翻译： 提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。 绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。 绝缘层基本上从半导体衬底表面升高。 升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。 形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

公开(公告)号：US08558278B2

公开(公告)日：2013-10-15

申请号：US11849798

申请日：2007-09-04

申请人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

摘要翻译： 应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。 在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。 优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。 优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。 此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

公开(公告)号：US08389348B2

公开(公告)日：2013-03-05

申请号：US12881505

申请日：2010-09-14

申请人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

发明人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chun Lin Tsai ,  Hsiao-Chin Tuan ,  Alex Kalnitsky

IPC分类号： H01L21/338

CPC分类号： H01L27/0617 ,  H01L21/26506 ,  H01L21/8258 ,  H01L27/085 ,  H01L2924/0002 ,  H01L2924/00

摘要： The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

摘要翻译： 在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。 通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。 在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。

公开(公告)号：US08368170B2

公开(公告)日：2013-02-05

申请号：US13367103

申请日：2012-02-06

申请人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L21/70

CPC分类号： H01L21/823475 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7846

摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。 第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。 第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。 该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

公开(公告)号：US08368136B2

公开(公告)日：2013-02-05

申请号：US12256132

申请日：2008-10-22

申请人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L27/04

CPC分类号： H01L27/0629 ,  H01L27/11 ,  H01L29/94

摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。 所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料 电极。

公开(公告)号：US08349680B2

公开(公告)日：2013-01-08

申请号：US12536629

申请日：2009-08-06

申请人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

发明人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Yu Chao Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/31645 ,  H01L21/31604 ,  H01L21/823842

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层 第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

公开(公告)号：US20120286368A1

公开(公告)日：2012-11-15

申请号：US13558109

申请日：2012-07-25

申请人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US20120228679A1

公开(公告)日：2012-09-13

申请号：US13475245

申请日：2012-05-18

申请人： Hong-Dyi Chang ,  Pei-Chao Su ,  Kong-Beng Thei ,  Hun-Jan Tao ,  Harry Hak-Lay Chuang

发明人： Hong-Dyi Chang ,  Pei-Chao Su ,  Kong-Beng Thei ,  Hun-Jan Tao ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28247 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.

摘要翻译： 公开了在接触形成期间保护栅极结构的各种方法。 一种示例性方法包括：在衬底上形成栅极结构，其中栅极结构包括栅极，栅极结构插入设置在衬底中的源极区域和漏极区域; 图案化第一蚀刻停止层，使得第一蚀刻停止层设置在源极区域和漏极区域上; 图案化第二蚀刻停止层，使得第二蚀刻停止层设置在栅极结构上; 以及形成源极接触，漏极接触和栅极接触，其中所述源极接触和所述漏极接触延伸穿过所述第一蚀刻停止层，并且所述栅极接触延伸穿过所述第二蚀刻停止层，其中形成所述源极接触， 漏极接触，并且栅极接触包括同时移除第一蚀刻停止层和第二蚀刻停止层以暴露栅极，源极区域和漏极区域。