公开(公告)号：US08378422B2

公开(公告)日：2013-02-19

申请号：US12609803

申请日：2009-10-30

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US08344416B2

公开(公告)日：2013-01-01

申请号：US12777672

申请日：2010-05-11

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

公开(公告)号：US20090101937A1

公开(公告)日：2009-04-23

申请号：US12342294

申请日：2008-12-23

申请人： Jian-Hsing Lee ,  Shui-Hunyi Chen

发明人： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC分类号： H01L29/73

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07420250B2

公开(公告)日：2008-09-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。

公开(公告)号：US20080174923A1

公开(公告)日：2008-07-24

申请号：US11812221

申请日：2007-06-15

申请人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

IPC分类号： H02H9/00 ,  H01L21/336

CPC分类号： H01L27/0255

摘要： A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

公开(公告)号：US07384802B2

公开(公告)日：2008-06-10

申请号：US11438603

申请日：2006-05-22

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L21/00

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US20080055802A1

公开(公告)日：2008-03-06

申请号：US11509998

申请日：2006-08-26

申请人： Chau-Neng Wu ,  Jian-Hsing Lee

发明人： Chau-Neng Wu ,  Jian-Hsing Lee

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An ESD protection circuit is implemented for a semiconductor device having a first circuit system operating with a first power supply voltage and a first complementary power supply voltage, and a second circuit system operating with a second power supply voltage and a second complementary power supply voltage. The ESD protection circuit includes a first diode having an anode coupled to the first power supply voltage and a cathode coupled to a first node connecting the first circuit system and the second circuit system for preventing a crosstalk of current between the first power supply voltage and the second complementary power supply voltage. A first MOS transistor module is coupled between the first node and the first complementary power supply for selectively creating a current path from the first node to the first complementary supply voltage for dissipating an ESD current during an ESD event.

公开(公告)号：US20070108527A1

公开(公告)日：2007-05-17

申请号：US11622574

申请日：2007-01-12

申请人： Jian-Hsing Lee ,  Shui Chen

发明人： Jian-Hsing Lee ,  Shui Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US20060284256A1

公开(公告)日：2006-12-21

申请号：US11157200

申请日：2005-06-17

申请人： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： The present invention provides a layout structure for an electrostatic discharge (ESD) protection circuit. The layout structure includes a first MOS device area, a second MOS device area, and a doped region. The first MOS device area has at least one source/drain region of a first polarity type. The second MOS device, which is adjacent to the first MOS device area, has at least one source/drain region of the first polarity type. A doped region of a second polarity type is interposed between the source/drain region of the first MOS device and the source/drain region of the second MOS device, such that the doped region and the source/drain regions interfacing therewith forming one or more diodes for dissipating ESD charges during an ESD event.

摘要翻译： 本发明提供了一种用于静电放电（ESD）保护电路的布局结构。 布局结构包括第一MOS器件区域，第二MOS器件区域和掺杂区域。 第一MOS器件区域具有至少一个第一极性类型的源极/漏极区域。 与第一MOS器件区域相邻的第二MOS器件具有至少一个第一极性类型的源极/漏极区域。 第二极性类型的掺杂区介于第一MOS器件的源极/漏极区域和第二MOS器件的源极/漏极区域之间，使得与其形成一个或多个的掺杂区域和源极/漏极区域 用于在ESD事件期间耗散ESD电荷的二极管。

公开(公告)号：US20060278928A1

公开(公告)日：2006-12-14

申请号：US11152440

申请日：2005-06-14

申请人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

发明人： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

摘要翻译： 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。