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129 条记录 (耗时 0.026 秒)

    Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect
    72.
    发明授权
    Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect 失效
    无位错局部氧化硅，抑制窄空间场氧化物稀化效应

    公开(公告)号：US06380610B1

    公开(公告)日：2002-04-30

    申请号：US09257838

    申请日：1999-02-25

    申请人： Igor V. Peidous ,  Elgin Quek ,  Konstantin V. Loiko ,  David Yeo Yong Hock

    发明人： Igor V. Peidous ,  Elgin Quek ,  Konstantin V. Loiko ,  David Yeo Yong Hock

    IPC分类号： H01L2358

    CPC分类号： H01L21/32 ,  H01L21/0332 ,  H01L21/76202 ,  Y10S438/95

    摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

    摘要翻译： 一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。 掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。 掩模在其下边缘处使用薄的氮化硅脚，以允许在氧化的早期阶段氧化物的标称膨胀，从而允许原位应力消除以及氧化物轮廓的平滑化。 第二较厚的氮化硅层的悬臂部分在生长速度减慢时在氧化的后期阶段抑制柔性脚的向上移动，由此抑制鸟喙的生长。 负责位错生成的剪切应力减少了五十倍。 这种应力降低伴随着表面形貌的改善以及窄的氧化物稀化效应的抑制。

    METHOD AND APPARATUS FOR UTILIZING CONTACT-SIDEWALL CAPACITANCE IN A SINGLE POLY NON-VOLATILE MEMORY CELL
    73.
    发明申请
    METHOD AND APPARATUS FOR UTILIZING CONTACT-SIDEWALL CAPACITANCE IN A SINGLE POLY NON-VOLATILE MEMORY CELL 审中-公开
    在单一非易失性存储器单元中使用接触式电容器的方法和装置

    公开(公告)号：US20130292756A1

    公开(公告)日：2013-11-07

    申请号：US13463514

    申请日：2012-05-03

    申请人： Yan Zhe Tang ,  Elgin Quek

    发明人： Yan Zhe Tang ,  Elgin Quek

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7883 ,  H01L27/11524 ,  H01L27/11558

    摘要： An approach for utilizing electrical capacitance between a plurality of contacts and sidewalls to provide voltage coupling between a floating gate (FG) and a control gate (CG) is disclosed. Embodiments include providing an FG and a CG laterally separated from each other; coupling a plurality of parallel polysilicon lines to the FG; providing a plurality of contacts between the plurality of the parallel polysilicon lines and coupling the contacts to the CG; and forming an electrical capacitance between the plurality of contacts and sidewalls of the plurality of parallel polysilicon lines to provide voltage coupling between the CG and the FG.

    摘要翻译： 公开了一种利用多个触点和侧壁之间的电容来提供浮动栅极（FG）和控制栅极（CG）之间的电压耦合的方法。 实施例包括提供彼此横向分离的FG和CG; 将多条平行多晶硅线耦合到FG; 在所述多个并行多晶硅线路之间提供多个触点，并将所述触点耦合到所述CG; 以及在多个并联多晶硅线的多个触点和侧壁之间形成电容，以提供CG与FG之间的电压耦合。

    Novel method to tune narrow width effect with raised S/D structure
    75.
    发明申请
    Novel method to tune narrow width effect with raised S/D structure 有权
    用提高的S / D结构调整窄宽度效应的新方法

    公开(公告)号：US20120007185A1

    公开(公告)日：2012-01-12

    申请号：US12803754

    申请日：2010-07-06

    申请人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    发明人： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/088 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/7848

    摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

    摘要翻译： 制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

    STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING
    76.
    发明申请
    STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING 审中-公开
    应变直接绝缘体（SDOI）基板和形成方法

    公开(公告)号：US20110278645A1

    公开(公告)日：2011-11-17

    申请号：US13191288

    申请日：2011-07-26

    申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    IPC分类号： H01L29/165

    CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

    摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

    摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

    Modulation of stress in stress film through ion implantation and its application in stress memorization technique
    79.
    发明授权
    Modulation of stress in stress film through ion implantation and its application in stress memorization technique 有权
    通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用

    公开(公告)号：US07592270B2

    公开(公告)日：2009-09-22

    申请号：US11940326

    申请日：2007-11-15

    申请人： Lee Wee Teo ,  Elgin Quek

    发明人： Lee Wee Teo ,  Elgin Quek

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/469 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

    摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。

    Modulation of Stress in Stress Film through Ion Implantation and Its Application in Stress Memorization Technique
    80.
    发明申请
    Modulation of Stress in Stress Film through Ion Implantation and Its Application in Stress Memorization Technique 有权
    通过离子注入调制应力薄膜的应力及其在应力记忆技术中的应用

    公开(公告)号：US20080064191A1

    公开(公告)日：2008-03-13

    申请号：US11940326

    申请日：2007-11-15

    申请人： Lee Wee Teo ,  Elgin Quek

    发明人： Lee Wee Teo ,  Elgin Quek

    IPC分类号： H01L21/425

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

    摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。