公开(公告)号：US20100307572A1

公开(公告)日：2010-12-09

申请号：US12713584

申请日：2010-02-26

申请人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Ghavam Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Ghavam Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/00 ,  H01L31/18

CPC分类号： H01L31/0304 ,  H01L21/20 ,  H01L21/76254 ,  H01L31/03762 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  H01L31/20 ,  Y02E10/548

摘要： A method for forming a heterojunction III-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer. A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

摘要翻译： 用于形成异质结III-V光伏（PV）电池的方法包括从III-V基片的晶片执行基底层的层转移，所述基底层小于约20微米厚; 在基层上形成本征层; 在本征层上形成非晶硅层; 以及在所述非晶硅层上形成透明导电氧化物层。 异质结III-V光伏（PV）电池包括包含III-V衬底的基层，所述基层小于约20微米厚; 位于基层上的本征层; 位于本征层上的非晶硅层; 以及位于非晶硅层上的透明导电氧化物层。

公开(公告)号：US20070235759A1

公开(公告)日：2007-10-11

申请号：US11401672

申请日：2006-04-11

申请人： William Henson ,  Yaocheng Liu ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana

发明人： William Henson ,  Yaocheng Liu ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana

IPC分类号： H01L31/00

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.

摘要翻译： 提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。 该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域 。 接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。 暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。 根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

公开(公告)号：US20070161214A1

公开(公告)日：2007-07-12

申请号：US11327675

申请日：2006-01-06

申请人： Jean Fompeyrine ,  Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  David Webb

发明人： Jean Fompeyrine ,  Edward Kiewra ,  Steven Koester ,  Devendra Sadana ,  David Webb

IPC分类号： H01L21/20 ,  H01L23/58

CPC分类号： H01L21/3205 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/28158 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/32051 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

摘要翻译： 提供了在III-V族化合物半导体的这种GaAs的表面上形成高k栅极叠层（介电常数大于二氧化硅的介电常数）的方法。 该方法包括使III-V族化合物半导体材料进行从III-V族化合物半导体材料的表面除去天然氧化物的预清洗工艺; 在III-V族化合物半导体材料的清洁表面上原位形成半导体，例如非晶Si层; 以及在所述半导体层上形成介电常数大于二氧化硅的电介质材料。 在一些实施例中，在形成电介质材料之前，半导体层被部分地或完全地转换成包括至少包括AO x N y Y y的表面层的层。 根据本发明，A是半导体材料，优选Si，x为0至1，y为0至1，x和y都不为零。

公开(公告)号：US20070090487A1

公开(公告)日：2007-04-26

申请号：US11259654

申请日：2005-10-26

申请人： Katherina Babich ,  Bruce Doris ,  David Medeiros ,  Devendra Sadana

发明人： Katherina Babich ,  Bruce Doris ,  David Medeiros ,  Devendra Sadana

IPC分类号： H01L21/76 ,  H01L31/11

CPC分类号： H01L29/0847 ,  H01L21/2236 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/7834

摘要： A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning via a novel surface preparation scheme, as well as a structure that results from the implementation of this scheme into the process integration flow for integrated circuitry are provided. The method of the present invention can by used for the selective or nonselective epitaxial growth of semiconductor material from the dissimilar surfaces. More specifically, the invention comprises a method for counterdoping of n-FET and/or p-FET regions of silicon circuitry during the halo and/or extension implantation process utilizing a technique by which the surface characteristics of the two regions are made similar with respect to their response to wet or dry surface preparation and which renders the two previously dissimilar surfaces amenable to simultaneous epitaxial growth of raised source/drain structures; but not otherwise affecting the electrical performance of the resulting device.

摘要翻译： 允许通过新颖的表面制备方案不使衬底变薄的不同掺杂的半导体表面（n型和p型）上的半导体材料均匀地同时外延生长的方法，以及由 提供了将该方案实现为集成电路的过程集成流程。 本发明的方法可以用于从不同的表面进行半导体材料的选择性或非选择性外延生长。 更具体地说，本发明包括一种在卤素和/或延伸注入过程期间用于对硅电路的n-FET和/或p-FET区进行反掺杂的方法，利用这样的技术，使两个区域的表面特性相对于 它们对湿表面或干表面制备的反应，并且使得两个先前不同的表面可以容易地升高的源极/漏极结构的同时外延生长; 但不会影响所得设备的电气性能。

公开(公告)号：US20060105559A1

公开(公告)日：2006-05-18

申请号：US10990300

申请日：2004-11-15

申请人： Tze-Chiang Chen ,  Bernard Meyerson ,  Devendra Sadana

发明人： Tze-Chiang Chen ,  Bernard Meyerson ,  Devendra Sadana

IPC分类号： H01L21/44

CPC分类号： H01L21/76243 ,  H01L21/31662

摘要： A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from about 100 angstroms to about 1 micron and annealing the substrate at a temperature from 1200° C. to 1400°0 C. in an oxygen containing atmosphere. The invention over comes the problem of the buried oxide breaking up into oxide islands during the anneal.

摘要翻译： 描述了一种用于形成超薄掩埋氧化物层的方法，其包括以下步骤：在厚度约10至约300埃厚的含硅衬底上形成含有Si的第一外延层，形成含有Si厚度的第二外延层 从约100埃至约1微米，并在含氧气氛中在1200℃至1400℃的温度下退火底物。 本发明是在退火期间埋入氧化物分解成氧化物岛的问题。

公开(公告)号：US20060105507A1

公开(公告)日：2006-05-18

申请号：US10992150

申请日：2004-11-18

申请人： Meikei Ieong ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Meikei Ieong ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/84

CPC分类号： H01L21/76251 ,  H01L21/2007

摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.

摘要翻译： 一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。 根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

公开(公告)号：US08703521B2

公开(公告)日：2014-04-22

申请号：US12713581

申请日：2010-02-26

申请人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L31/068 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548

摘要： A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.

摘要翻译： 制造多结光伏（PV）电池的方法包括在衬底上提供包括多个结的叠层，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最小带隙的结点排序 位于具有最大带隙位于堆叠顶部的基底上的基底上; 在具有最大带隙的结的顶部上形成顶部金属层，顶部金属层具有拉伸应力; 将顶部柔性基底粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于顶部金属层中的拉伸应力形成断裂。

公开(公告)号：US08536043B2

公开(公告)日：2013-09-17

申请号：US13017127

申请日：2011-01-31

申请人： Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

发明人： Jeehwan Kim ,  Jin-Hong Park ,  Devendra Sadana ,  Kuen-Ting Shiu

IPC分类号： H01L21/28

CPC分类号： H01L29/20 ,  H01L21/26513 ,  H01L21/28575 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/78

摘要： Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant. The electrical contact can be a source or a drain contact of a transistor.

摘要翻译： 本发明的实施例提供一种制造电接触的方法。 该方法包括提供化合物III-V族半导体材料的衬底，其具有与衬底的表面相邻的至少一个导电掺杂区域。 该方法还包括通过在衬底的表面上沉积锗的单晶层以至少部分地覆盖在至少一个导电掺杂区域上来将至少一个导电掺杂区域的电接触制造到该至少一个导电掺杂区域， 通过注入掺杂剂，在非晶锗层的暴露表面上形成金属层，并对具有上覆金属层的非晶锗层进行金属诱导结晶（MIC）工艺，将锗的晶体层分解成无定形锗层， 将无定形锗层转化为结晶锗层并激活注入的掺杂剂。 电接触可以是晶体管的源极或漏极接触。

公开(公告)号：US20120282782A1

公开(公告)日：2012-11-08

申请号：US13480329

申请日：2012-05-24

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra Sadana

IPC分类号： H01L21/30

CPC分类号： H01L31/0304 ,  H01L21/20 ,  H01L21/76254 ,  H01L31/03762 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  H01L31/20 ,  Y02E10/548

摘要： Manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. The stress layer may comprise a flexible material.

摘要翻译： 制造薄膜直接带隙半导体活性太阳能电池器件包括提供具有表面的源极衬底，并且在表面上设置应力层，其应力层表面积与源极衬底的表面接触并结合。 将手柄箔与应力层操作地相关联并且向手柄箔施加力将应力层与源衬底分离，并将源衬底的一部分留在应力层表面上，基本上对应于与表面相接触的区域 源底物。 该部分的厚度不如源层厚。 应力层厚度低于导致源底材自发剥落的厚度。 源极衬底可以包括无机单晶或多晶材料，例如Si，Ge，GaAs，SiC，蓝宝石或GaN。 应力层可以包括柔性材料。

公开(公告)号：US20110048517A1

公开(公告)日：2011-03-03

申请号：US12713592

申请日：2010-02-26

申请人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi

IPC分类号： H01L31/101 ,  H01L31/18

CPC分类号： H01L31/0735 ,  H01L21/02002 ,  H01L31/0304 ,  H01L31/03046 ,  H01L31/0725 ,  H01L31/1808 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/521

摘要： A method for fabrication of a multijunction photovoltaic (PV) cell includes forming a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the largest bandgap being located on the substrate to the junction having the smallest bandgap being located on top of the stack; forming a metal layer, the metal layer having a tensile stress, on top of the junction having the smallest bandgap; adhering a flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the metal layer.

摘要翻译： 一种制造多结光伏（PV）电池的方法包括在衬底上形成包括多个结的叠层，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最大带隙的结点排序 位于具有最小带隙位于堆叠顶部的基底上的基底上; 在具有最小带隙的结的顶部上形成具有拉伸应力的金属层; 将柔性基板粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于金属层中的拉伸应力而形成断裂。