公开(公告)号：US20060284276A1

公开(公告)日：2006-12-21

申请号：US11157601

申请日：2005-06-21

申请人： Hamza Yilmaz

发明人： Hamza Yilmaz

IPC分类号： H01L23/58

CPC分类号： H01L29/7393 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high-voltage field-effect device contains an extended drain or “drift” region having a plurality of JFET regions separated by portions of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and at least two sides of each JFET region is lined with an oxide layer. In one group of embodiments the JFET regions extend from the surface of an epitaxial layer to an interface between the epitaxial layer and an underlying substrate, and the walls of each JFET region are lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region and allowing the JFET regions to be accurately located in the drift region.

公开(公告)号：US20060170036A1

公开(公告)日：2006-08-03

申请号：US11375975

申请日：2006-03-14

申请人： Hamza Yilmaz

发明人： Hamza Yilmaz

IPC分类号： H01L31/113

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8605 ,  H01L29/872

摘要： A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

摘要翻译： 半导体器件包括与衬底的导电性相反地掺杂的场屏蔽区域，并且被电介质侧壁间隔物横向限定，并由下面由PN结限定。 例如，在沟槽门控MOSFET中，场屏蔽区域可以位于沟槽下方并且可以电连接到源极区域。 当MOSFET被反向偏置时，耗尽区从电介质侧壁间隔物延伸到“漂移”区域中，屏蔽栅极氧化物免受高电场和增加器件的雪崩击穿电压。 这允许漂移区域被更加重掺杂并降低器件的导通电阻。 它还允许使用薄的20Å栅极氧化物作为功率MOSFET，其将被施加到其栅极上的1V信号切换，同时能够阻挡超过30V施加在其漏极和源电极上。

公开(公告)号：US20060125045A1

公开(公告)日：2006-06-15

申请号：US11352633

申请日：2006-02-13

申请人： Hamza Yilmaz

发明人： Hamza Yilmaz

IPC分类号： H01L29/00

CPC分类号： H01L21/743 ,  H01L21/763 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0821 ,  H01L29/7322 ,  H01L29/7835

摘要： A semiconductor structure includes a trench formed in an epitaxial layer that overlies a semiconductor substrate, the sides of the trench being lined with an oxide layer. The trench is filled with a conductive material, e.g., a metal or heavily-doped polysilicon, and the conductive is in contact with the substrate or a doped region in the substrate or epitaxial layer. The structure expands far less horizontally than conventional diffusions and therefore allows a higher packing density of devices formed in the epitaxial layer. The structure may be used in place of conventional sinkers and isolation diffusions.

摘要翻译： 半导体结构包括形成在半导体衬底上的外延层中形成的沟槽，沟槽的侧面衬有氧化物层。 沟槽填充有导电材料，例如金属或重掺杂多晶硅，并且导电层与衬底或衬底或外延层中的掺杂区域接触。 该结构比常规扩散水平地扩展得更少，因此允许在外延层中形成的器件具有较高的堆积密度。 可以使用该结构来代替常规的沉降片和隔离扩散。

公开(公告)号：US5648281A

公开(公告)日：1997-07-15

申请号：US647073

申请日：1996-05-08

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun Wei Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun Wei Chen

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/014 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种同时形成双极晶体管，相对高压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器的方法（以下称为“BiCDMOS工艺”），或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5614751A

公开(公告)日：1997-03-25

申请号：US632052

申请日：1996-04-15

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L27/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7397 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

摘要翻译： 用于沟槽MOSFET或其他半导体器件的端接结构（沿着晶体管周边或管芯边缘）防止不期望的表面沟道现象，而不需要任何额外的掩蔽步骤来形成通道停止。 这种结构特别适用于P沟道MOSFET。 在现有技术中，掩模限定掺杂通道阻挡。 而是在有源区域掩蔽处理之后进行P型离子的覆盖离子注入。 因此，在由场氧化物制造期间，该掺杂沟道停止终止实际上被掩蔽。 在另一个版本中，通道停止端接是在MOSFET的端接区域中形成的另外的沟槽。 沟槽通常衬有氧化物，并填充有延伸到模具边缘的导电多晶硅场板。 在另一个版本中，掺杂和沟槽通道停止组合使用。 通过在模具表面上提供覆盖它们的场板来增强通道停止。

公开(公告)号：US5559044A

公开(公告)日：1996-09-24

申请号：US323950

申请日：1994-10-17

申请人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

发明人： Richard K. Williams ,  Hamza Yilmaz ,  Michael E. Cornell ,  Jun W. Chen

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0635 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  Y10S148/082 ,  Y10S148/126 ,  Y10S438/983

摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。

公开(公告)号：US5517379A

公开(公告)日：1996-05-14

申请号：US67373

申请日：1993-05-26

申请人： Richard K. Williams ,  Thomas Toombs ,  King Owyang ,  Hamza Yilmaz

发明人： Richard K. Williams ,  Thomas Toombs ,  King Owyang ,  Hamza Yilmaz

IPC分类号： H02H11/00 ,  H02H9/00

CPC分类号： H02H11/003 ,  Y10T307/839

摘要： A device for protecting battery-powered semiconductor devices and the like against a reverse battery condition. During normal operation a charge pump charges the gate of a power MOSFET, turning the MOSFET on and providing a low-resistance power supply path from the battery to the load. If the battery is reversed, a depletion mode device shorts the gate and source of the MOSFET, turning it off and disconnecting the load from the battery.

摘要翻译： 一种用于防止反向电池状况的电池供电的半导体器件等的装置。 在正常运行期间，电荷泵为功率MOSFET的栅极充电，使MOSFET导通，并提供从电池到负载的低电阻电源路径。 如果电池反转，耗尽型器件会损坏MOSFET的栅极和源极，将其关闭并断开负载与电池的连接。

公开(公告)号：US5430314A

公开(公告)日：1995-07-04

申请号：US873423

申请日：1992-04-23

申请人： Hamza Yilmaz

发明人： Hamza Yilmaz

IPC分类号： H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L27/14 ,  H01L31/00

CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/7802 ,  H01L29/7811

摘要： The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

摘要翻译： 本发明提供了栅极屏蔽区域和功率器件的有源电池之间的栅极缓冲区域。 该栅极缓冲区可以例如是从外延层的上表面延伸到外延层中的相对窄的带状掺杂区域。 栅极屏蔽区域通过相对高阻抗的连接与功率器件的源极连接。 另一方面，栅极缓冲区域以相对较低的阻抗连接与源极连接。 该相对低阻抗的连接例如可以是从外围层的表面处的金属源电极到栅极缓冲区域的基本上直接的金属化连接。

公开(公告)号：US5429964A

公开(公告)日：1995-07-04

申请号：US180265

申请日：1994-01-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US12087831B2

公开(公告)日：2024-09-10

申请号：US18077731

申请日：2022-12-08

申请人： TAIWAN SEMICONDUCTOR CO., LTD. ,  Hamza Yilmaz

发明人： Hamza Yilmaz ,  Aryadeep Mrinal

IPC分类号： H01L29/40 ,  H01L21/265 ,  H01L29/06

CPC分类号： H01L29/404 ,  H01L21/265 ,  H01L29/0638

摘要： A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.