公开(公告)号：US11114405B2

公开(公告)日：2021-09-07

申请号：US16725190

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hua Chang ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC: H01L21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.

公开(公告)号：US11101252B2

公开(公告)日：2021-08-24

申请号：US16548817

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Chin-Fu Kao ,  Jing-Cheng Lin ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2

公开(公告)号：US20210210400A1

公开(公告)日：2021-07-08

申请号：US17208694

申请日：2021-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US20210125900A1

公开(公告)日：2021-04-29

申请号：US17142190

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Ku-Feng Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

公开(公告)号：US20210028097A1

公开(公告)日：2021-01-28

申请号：US17068310

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

公开(公告)号：US20200373264A1

公开(公告)日：2020-11-26

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

公开(公告)号：US20200373215A1

公开(公告)日：2020-11-26

申请号：US16989047

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/10 ,  H01L23/14 ,  H01L23/16 ,  H01L23/28 ,  H01L23/433 ,  H01L23/48 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

公开(公告)号：US10518387B2

公开(公告)日：2019-12-31

申请号：US15652244

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Jing-Cheng Lin ,  Wen-Hua Chang

IPC: B24D7/06 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

Abstract: A grinding element mounted on a grinding wheel and a grinding wheel containing the same are provided for grinding. The grinding element includes a grinding tooth, and the grinding tooth includes a grinding material having a framework structure and pores distributed in the framework structure. The framework structure includes a bond material and abrasive particles that are bonded by the bond material. A pore size of the pores is larger than 40 microns but smaller than 70 microns. A manufacturing method for semiconductor packages using the same is also provided.

公开(公告)号：US20190027446A1

公开(公告)日：2019-01-24

申请号：US15652247

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component. The conductive terminals are disposed on and electrically connected to the protruding portions of the conductive through vias, and a plurality of intermetallic compound caps are formed between the conductive terminals and the protruding portions.

公开(公告)号：US20190022827A1

公开(公告)日：2019-01-24

申请号：US15652244

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Jing-Cheng Lin ,  Wen-Hua Chang

IPC: B24D7/06 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

Abstract: A grinding element mounted on a grinding wheel and a grinding wheel containing the same are provided for grinding. The grinding element includes a grinding tooth, and the grinding tooth includes a grinding material having a framework structure and pores distributed in the framework structure. The framework structure includes a bond material and abrasive particles that are bonded by the bond material. A pore size of the pores is larger than 40 microns but smaller than 70 microns. A manufacturing method for semiconductor packages using the same is also provided.