公开(公告)号：US11025033B2

公开(公告)日：2021-06-01

申请号：US16417712

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/183 ,  H01S5/02375 ,  H01S5/42 ,  H01S5/0237 ,  H01S5/30

Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.

公开(公告)号：US11005037B2

公开(公告)日：2021-05-11

申请号：US15647579

申请日：2017-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

公开(公告)号：US20210091538A1

公开(公告)日：2021-03-25

申请号：US16579692

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/183

Abstract: In some embodiments, the present disclosure relates to a vertical cavity surface emitting laser (VCSEL) device that includes a microlens arranged over a reflector stack. The reflector stack comprises alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer comprises a first average concentration of a first element and has a first width. The second lens layer comprises a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer comprises a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

公开(公告)号：US20210082866A1

公开(公告)日：2021-03-18

申请号：US16568605

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01L25/075 ,  H01L33/00 ,  H01L33/62 ,  H01S5/18

Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.

公开(公告)号：US20200321348A1

公开(公告)日：2020-10-08

申请号：US16909066

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu

IPC: H01L27/11556 ,  H01L29/423 ,  H01L27/1158 ,  H01L29/66 ,  G11C16/04

Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

公开(公告)号：US20200227426A1

公开(公告)日：2020-07-16

申请号：US16387720

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11548 ,  H01L21/762 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L21/311

Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.

公开(公告)号：US20200076162A1

公开(公告)日：2020-03-05

申请号：US16122018

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen Yu Chen ,  Ming Chyi Liu ,  Jhih-Bin Chen

IPC: H01S5/183 ,  H01S5/02 ,  H01S5/187 ,  H01S5/20 ,  H01S5/028

Abstract: Some embodiments relate to a method for manufacturing a vertical cavity surface emitting laser. The method includes forming an optically active layer over a first reflective layer and forming a second reflective layer over the optically active layer. Forming a masking layer over the second reflective layer, where the masking layer leaves a sacrificial portion of the second reflective layer exposed. A first etch is performed to remove the sacrificial portion of the second reflective layer, defining a second reflector. Forming a first spacer covering outer sidewalls of the second reflector and masking layer. An oxidation process is performed with the first spacer in place to oxidize a peripheral region of the optically active layer while leaving a central region of the optically active layer un-oxidized. A second etch is performed to remove a portion of the oxidized peripheral region, defining an optically active region. Forming a second spacer covering outer sidewalls of the first spacer, the optically active region, and the first reflector.

公开(公告)号：US20200044039A1

公开(公告)日：2020-02-06

申请号：US16420469

申请日：2019-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu

IPC: H01L29/423 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/84

Abstract: An integrated circuit includes a SOI substrate comprising a base substrate, an insulator layer, and a semiconductor device layer. Source and drain regions in the semiconductor device layer are spaced apart by a channel region in the semiconductor device layer. A gate electrode is disposed over the channel region and has a bottom surface that extends below a top surface of the semiconductor device layer. A sidewall spacer structure extends along outer sidewalls of the gate electrode and has a bottom surface that rests on the top surface of the semiconductor device layer. A gate dielectric separates the channel region from the bottom surface of the gate electrode and contacts the bottom surface of the sidewall spacer structure. The channel region beneath the bottom surface of the gate electrode corresponds to the semiconductor device layer and has a thickness of less than 40 angstroms.

公开(公告)号：US10535671B2

公开(公告)日：2020-01-14

申请号：US16506207

申请日：2019-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L21/762 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US20200006271A1

公开(公告)日：2020-01-02

申请号：US16025046

申请日：2018-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Chia-Shiung Tsai ,  Ming Chyi Liu ,  Eugene Chen

IPC: H01L23/00 ,  H01S5/183 ,  H01S5/343 ,  H01S5/022

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.