公开(公告)号：US20220189919A1

公开(公告)日：2022-06-16

申请号：US17688448

申请日：2022-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

公开(公告)号：US11328971B2

公开(公告)日：2022-05-10

申请号：US16939341

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng ,  Chih-Kung Huang ,  Tsung-Ming Yeh

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/04 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18

Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

公开(公告)号：US11270953B2

公开(公告)日：2022-03-08

申请号：US16284630

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng ,  Shuo-Mao Chen ,  Ming-Chih Yew

IPC: H01L23/552 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H05K1/02 ,  H01L23/498 ,  H01L25/16 ,  H01L23/00

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

公开(公告)号：US11264300B2

公开(公告)日：2022-03-01

申请号：US16182750

申请日：2018-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Chin-Hua Wang

IPC: H01L23/367 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.

公开(公告)号：US11239173B2

公开(公告)日：2022-02-01

申请号：US16446796

申请日：2019-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Techi Wong ,  Shin-Puu Jeng

IPC: H01L21/98 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

公开(公告)号：US20210375789A1

公开(公告)日：2021-12-02

申请号：US17401616

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Clinton Chao ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/302 ,  H01L23/52 ,  H01L21/56 ,  H01L21/78 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

公开(公告)号：US11189596B2

公开(公告)日：2021-11-30

申请号：US16928003

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US20210351118A1

公开(公告)日：2021-11-11

申请号：US17383953

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US11094625B2

公开(公告)日：2021-08-17

申请号：US16406600

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Techi Wong ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Shih-Ting Hung ,  Shin-Puu Jeng

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

公开(公告)号：US20210090906A1

公开(公告)日：2021-03-25

申请号：US17099180

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Tsai ,  Tsung-Shang Wei ,  Yu-Sheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/60 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/16 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.