公开(公告)号：US07132847B1

公开(公告)日：2006-11-07

申请号：US10708303

申请日：2004-02-24

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC: H03K19/003

CPC classification number: H03K17/6872 ,  H03K17/164

Abstract: A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.

Abstract translation: 可编程技术用于控制差分输出缓冲器的转换速率。 一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。 这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。 后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。 具体应用是可编程逻辑集成电路的差分输出。

公开(公告)号：US07109744B1

公开(公告)日：2006-09-19

申请号：US11226710

申请日：2005-09-13

Applicant: Sergey Shumarayev ,  Thomas White

Inventor： Sergey Shumarayev ,  Thomas White

IPC: H03K19/0175

CPC classification number: H04L25/0298

Abstract: Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

Abstract translation: 用于实现具有高度灵活的接口电路的电路和系统的各种实施例，其能够实现可编程的片上终止和DC电平控制。 许多技术使用现有的I / O资源实现可编程片上终止和DC电平控制，使集成电路能够满足各种不同的高速单端和差分I / O标准。

公开(公告)号：US06888370B1

公开(公告)日：2005-05-03

申请号：US10645932

申请日：2003-08-20

Applicant: Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC: H03K19/0175 ,  H04L25/02

CPC classification number: H04L25/0278

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract translation: 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

公开(公告)号：US06593772B2

公开(公告)日：2003-07-15

申请号：US10177785

申请日：2002-06-19

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel ,  Tin Lai

IPC: H03K19177

CPC classification number: G11C5/025 ,  H03K19/17736 ,  H03K19/1776

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

公开(公告)号：US06407576B1

公开(公告)日：2002-06-18

申请号：US09516921

申请日：2000-03-02

Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC: H01L2500

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：US06239615B1

公开(公告)日：2001-05-29

申请号：US09235371

申请日：1999-01-20

Applicant: Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

Inventor： Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

IPC: H03K19177

CPC classification number: H03K19/17736 ,  H01L23/5222 ,  H01L2924/0002 ,  H03K19/1778 ,  H03K19/17792 ,  H03K19/17796 ,  H01L2924/00

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract translation: 为集成电路提供高性能互连的技术将提高整体集成电路性能。 这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。 这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

公开(公告)号：US10110328B2

公开(公告)日：2018-10-23

申请号：US13446555

申请日：2012-04-13

Applicant: Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

Inventor： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC: G01R35/00 ,  H04B17/21 ,  H04B17/11 ,  G12B13/00

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US09559881B2

公开(公告)日：2017-01-31

申请号：US12283652

申请日：2008-09-15

Applicant: Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

Inventor： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC: H04L7/00 ,  H04B1/38 ,  H04L25/14

CPC classification number: H04L25/14

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Abstract translation: 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US09429625B1

公开(公告)日：2016-08-30

申请号：US13475256

申请日：2012-05-18

Applicant: Weiqi Ding ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Sergey Shumarayev

IPC: G01R31/00 ,  G01R31/319 ,  G01R31/40

CPC classification number: G01R31/31924 ,  G01R31/3167 ,  G01R31/40

Abstract: An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.

Abstract translation: 模拟测试网络包括导体。 导体被耦合以从被测电路提供到模拟 - 数字转换器电路的第一模拟信号。 模数转换器电路可操作以基于第一模拟信号产生第一数字信号。 控制电路可操作以基于第一数字信号产生第二数字信号。 数模转换器电路可操作以基于第二数字信号产生第二模拟信号。 导体被耦合以将第二模拟信号从数模转换器电路提供给被测电路。

公开(公告)号：US08976804B1

公开(公告)日：2015-03-10

申请号：US13041764

申请日：2011-03-07

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H04L12/66

CPC classification number: H03K19/17744

Abstract: In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

Abstract translation: 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。