公开(公告)号：US06290264B1

公开(公告)日：2001-09-18

申请号：US09791709

申请日：2001-02-26

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： F16L3500

CPC分类号： F16L37/0987 ,  F16L3/02 ,  Y10S285/921

摘要： A resin tube 9 inserted and fixed to one end of a female connector 10 and a corresponding pipe 11 connected by snap in to the other end of a female connector 10 are fixed by a first holding means 17 and a second holding means 18 of a holder member 16 respectively. Holding portion of either the resin tube 9 and the corresponding pipe 11 is located off the common axis L as securely held by the holder member 16. Either the resin tube 9 or the corresponding pipe 11 is turned about the female connector 10 so as to connect with either the first holding means 17 or the second holding means 18.

摘要翻译： 插入并固定到阴连接器10的一端的树脂管9和通过卡入阴连接器10的另一端连接的相应管11由第一保持装置17和保持器的第二保持装置18固定 成员16。 树脂管9和相应管11的保持部分位于由保持件16牢固地保持的公共轴线L之外。树脂管9或相应的管11都绕阴连接器10转动以便连接 第一保持装置17或第二保持装置18。

公开(公告)号：US6037632A

公开(公告)日：2000-03-14

申请号：US744212

申请日：1996-11-05

申请人： Ichiro Omura ,  Tomoki Inoue ,  Hiromichi Ohashi

发明人： Ichiro Omura ,  Tomoki Inoue ,  Hiromichi Ohashi

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/70 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/74 ,  H01L23/58 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/74 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66712 ,  H01L29/739 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/872 ,  H01L29/41775 ,  H01L2924/0002

摘要： A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least a buried layer of second conductivity type selectively formed in the semiconductor layer, extending at substantially right angles to a line connecting the first and second main electrodes, comprising a plurality strips functioning as current paths and set at a potential different from a potential of any other electrode when a depletion layer extending from a region near the first main electrode reaches the buried layer.

摘要翻译： 公开了一种半导体器件，其包括第一主电极，第二主电极，插入在第一主电极和第二主电极之间的第一导电类型的高电阻半导体层，以及至少第二导电类型的掩埋层 选择性地形成在半导体层中，以与连接第一和第二主电极的线基本成直角延伸，包括用作电流路径的多个条带，并且当从第一和第二主电极延伸的耗尽层设置为与任何其它电极的电位不同的电位时 第一主电极附近的区域到达掩埋层。

公开(公告)号：US5838026A

公开(公告)日：1998-11-17

申请号：US827530

申请日：1997-03-28

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L21/36

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5585651A

公开(公告)日：1996-12-17

申请号：US487508

申请日：1995-06-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括p型发射极层，在P型发射极层上形成的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5448083A

公开(公告)日：1995-09-05

申请号：US261384

申请日：1994-06-15

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L21/36 ,  H01L21/74

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面上形成与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US08609200B2

公开(公告)日：2013-12-17

申请号：US12418711

申请日：2009-04-06

申请人： Tomoki Inoue ,  Kazutaka Katayama

发明人： Tomoki Inoue ,  Kazutaka Katayama

IPC分类号： H05H1/24 ,  B05D3/06 ,  B05D3/12 ,  H05H1/46

CPC分类号： B29C57/00 ,  B29C59/103 ,  F16L33/34 ,  F16L47/24 ,  Y10T428/1393

摘要： In a hose having a resin layer as an inner layer, a plasma treatment is performed on the inner surface of the inner layer and a connecting portion of an end part of the hose to thereby perform surface modification. Then, a sealing layer made of an elastic material is coated on and bonded to the inner surface of the connecting portion.

摘要翻译： 在具有树脂层作为内层的软管中，在内层的内表面和软管的端部的连接部分进行等离子体处理，从而进行表面改性。 然后，将由弹性材料制成的密封层涂覆在粘合到连接部分的内表面上。

公开(公告)号：US07642599B2

公开(公告)日：2010-01-05

申请号：US11331160

申请日：2006-01-13

申请人： Hideaki Ninomiya ,  Tomoki Inoue

发明人： Hideaki Ninomiya ,  Tomoki Inoue

IPC分类号： H01L23/62 ,  H01L27/088

CPC分类号： H01L29/404 ,  H01L29/0619 ,  H01L29/0692 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。

公开(公告)号：US07316428B2

公开(公告)日：2008-01-08

申请号：US10679747

申请日：2003-10-06

申请人： Akira Takayanagi ,  Tomoki Inoue

发明人： Akira Takayanagi ,  Tomoki Inoue

IPC分类号： F16L21/06 ,  F16L35/00

CPC分类号： F16L3/1226 ,  F16L37/0987 ,  F16L2201/10 ,  Y10S285/921

摘要： Connection verifying device for a pipe and a connector has a body portion, a stop and verification arm and an abutment finger. The body portion includes an abutment plate and a fit-on portion. The stop and verification arm extends from an outer periphery of the abutment plate in one axial direction, while the abutment finger protrudes from one axial end of the fit-on portion in one axial direction. The abutment finger is arranged so as to abut and urge an annular projection of a pipe into an engagement slit of a retainer when the pipe and the connector are in half-fitting relation.

摘要翻译： 用于管道和连接器的连接验证装置具有主体部分，停止和验证臂以及邻接手指。 主体部分包括邻接板和装配部分。 停止和验证臂在一个轴向方向上从邻接板的外周延伸，同时邻接指状物在一个轴向方向上从装配部分的一个轴向端部突出。 当管和连接器处于半配合关系时，邻接指状物被布置成邻接和推动管道的环形突起到保持器的接合狭缝中。

公开(公告)号：US20070241376A1

公开(公告)日：2007-10-18

申请号：US11785199

申请日：2007-04-16

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： H01L31/113

CPC分类号： H01L27/14812 ,  H01L27/14647

摘要： A solid-state imaging device is provided and includes: a semiconductor substrate; a plurality of photoelectric conversion films stacked above the semiconductor layer and absorbing different wavelength regions of light; and a transmission-blocking film at least one between the plurality of photoelectric conversion films, the transmission-blocking film blocking a transmission of a particular region of light, the particular region of light having a wavelength in a region to be absorbed in a photoelectric conversion film located above and nearest to the transmission-blocking film.

摘要翻译： 提供了一种固态成像器件，包括：半导体衬底; 多个光电转换膜，堆叠在半导体层上方并吸收光的不同波长区域; 以及在所述多个光电转换膜之间的至少一个传输阻挡膜，所述透射阻挡膜阻挡特定区域的透射，所述特定区域的光在要被光电转换中吸收的区域中具有波长 膜位于传播阻挡膜的上方且最靠近。

公开(公告)号：US20070096849A1

公开(公告)日：2007-05-03

申请号：US11537842

申请日：2006-10-02

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： H03H7/01

CPC分类号： H03H1/0007 ,  H01L23/552 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： EMI filter 20 includes input terminal Vin, output terminal Vout, resistor component R1 and diodes D1 and D2. Resistor component R1 is composed of polycrystalline resistor component Rp and ring resistor components R11 and R12. Polycrystalline resistor component Rp is connected between input and output terminals Vin and Vout. Ring resistor components R11 and R12 are provided on one and the other sides of polycrystalline resistor component at a prescribed distance, respectively. Further, diode D1 has cathode and anode electrodes connected to input terminal Vin and reference potential Vss, respectively. Likewise, diode D2 has cathode and anode electrodes connected to output terminal Vout and reference potential Vss, respectively. Ring resistor components R11 and R12 are rectangular in shape to electromagnetically couple to polycrystalline resistor component Rp. When a high frequency signal is applied to input terminal Vin, an electric current flowing through polycrystalline resistor component Rp generates magnetic fields so that ring resistor components R11 and R12 electro-magnetically induce an electric current.

摘要翻译： EMI滤波器20包括输入端子Vin，输出端子Vout，电阻器部件R 1和二极管D1和D2。电阻器部件R 1由多晶电阻器部件Rp和环形电阻器部件R 11和R 12组成。多晶电阻器部件Rp是 连接在输入和输出端子Vin和Vout之间。 环状电阻器部件R 11和R 12分别以规定距离设置在多晶电阻器部件的一侧和另一侧上。 此外，二极管D1分别具有连接到输入端Vin和参考电位Vss的阴极和阳极电极。 同样，二极管D 2分别具有连接到输出端Vout和参考电位Vss的阴极和阳极电极。 环形电阻器部件R 11和R 12的形状为矩形，以电磁耦合到多晶电阻器部件Rp。 当向输入端子Vin施加高频信号时，流过多晶硅电阻器部件Rp的电流产生磁场，使得环形电阻器部件R 11和R 12电磁感应出电流。