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77 条记录 (耗时 0.018 秒)

    Method for modification of fats and oils
    71.
    发明授权
    Method for modification of fats and oils 失效
    脂肪和油的改性方法

    公开(公告)号：US4420560A

    公开(公告)日：1983-12-13

    申请号：US322248

    申请日：1981-11-17

    申请人： Takaharu Matsuo ,  Norio Sawamura ,  Yukio Hashimoto ,  Wataru Hashida

    发明人： Takaharu Matsuo ,  Norio Sawamura ,  Yukio Hashimoto ,  Wataru Hashida

    IPC分类号： A23G1/00 ,  A23G1/38 ,  A23G1/56 ,  C11C3/08 ,  C11C3/10 ,  C12P7/64

    CPC分类号： A23G1/38 ,  A23G1/56 ,  C11C3/08 ,  C11C3/10 ,  C12P7/6409 ,  C12P7/6436 ,  C12P7/6454 ,  A23G2200/08

    摘要： In a method of the modification of a fat or oil wherein a mixture (mixture A) containing a glyceride-type fat or oil to be modified (material A) and a fatty acid or a nonglyceride-type ester thereof (material B) is selectively transesterified in the presence of a catalyst having a selective transesterification activity (catalyst A); the resulting fat or oil (resultant A), fatty acid or nonglyceride-type ester thereof (resultant B) and catalyst are recovered from the reaction mixture; and then a hard butter is produced from the resultant A, the improvement comprises hydrogenating a part or all of the resultant B and reusing the hydrogenated product as a part of the mixture A.

    摘要翻译： 在脂肪或油的改性方法中，其中含有甘油酯型脂肪或油（待改性物质A）和脂肪酸或其不饱和脂肪酸酯（材料B）的混合物（混合物A）是选择性的 在具有选择性酯交换活性的催化剂存在下酯交换（催化剂A）; 从反应混合物中回收所得的脂肪或油（所得的A），脂肪酸或其非农性脂肪酸酯（得到的B）和催化剂; 然后从得到的A产生硬质的黄油，改进包括氢化部分或全部所得的B，并重新使用氢化产物作为混合物A的一部分。

    Voltage control circuit responsive to FET propagation time
    72.
    发明授权
    Voltage control circuit responsive to FET propagation time 失效
    电压控制电路响应FET传播时间

    公开(公告)号：US4358728A

    公开(公告)日：1982-11-09

    申请号：US129829

    申请日：1980-03-13

    申请人： Yukio Hashimoto

    发明人： Yukio Hashimoto

    IPC分类号： G04G3/00 ,  G04C10/00 ,  G04G19/06 ,  G05F1/46 ,  G05F3/24 ,  G05F1/58

    CPC分类号： G05F1/463 ,  G04G19/06 ,  Y10S323/907 ,  Y10S331/03

    摘要： An electronic timepiece contains a supply voltage source which provides a supply voltage controlled in accordance with temperature, whereby power consumption is reduced by supplying the timepiece circuit with only the amplitude of supply voltage required at any particular operating temperature. Voltage control is performed in accordance with variations in propagation times of circuit elements with temperature, as determined by variations in the frequency of a ring oscillator circuit.

    摘要翻译： 电子钟表包含提供根据温度控制的电源电压的电源电压源，通过仅在时钟电路提供在任何特定工作温度下所需的电源电压的幅度来降低功耗。 根据环路振荡器电路的频率变化所确定的，根据具有温度的电路元件的传播时间的变化执行电压控制。

    Electronic timepiece
    77.
    发明授权
    Electronic timepiece 失效
    电子钟表

    公开(公告)号：US4015419A

    公开(公告)日：1977-04-05

    申请号：US658037

    申请日：1976-02-13

    申请人： Shigeru Morokawa ,  Yukio Hashimoto

    发明人： Shigeru Morokawa ,  Yukio Hashimoto

    IPC分类号： G04F5/06 ,  G04G3/02 ,  G06F7/68 ,  G04C3/00

    CPC分类号： G04F5/06 ,  G04G3/022 ,  G06F7/68

    摘要： To facilitate acceleration or deceleration of the stepping rate of a time-keeping counter responding to driving pulses from a frequency divider connected to a crystal-controlled oscillator, a succession of such driving pulses is taken from an OR gate with inputs receiving a basic pulse train .phi..sub..gamma. a normally present first ancillary pulse train .phi..sub..beta. spacedly interleaved with pulse train .phi..sub..gamma. and a normally absent second ancillary pulse train .phi..sub..alpha. with pulse positions offset from those of the other two pulse trains. To retard the timepiece, the pulses of train .phi..sub..beta. are blocked for a desired period; to advance it, pulses of train .phi..sub..alpha. are interpolated at a rate depending on the cadence of a series of control pulses selectively synthesized from a combination of low-frequency stage outputs of the frequency divider. Externally set selection signals are temporarily stored in a memory circuit including NOR gates with positive-feedback connections to inverting inputs thereof, the memory circuit being periodically tested by a resetting pulse recurring at a frequency lower than that of the driving pulses.

    摘要翻译： 为了便于对来自连接到晶体振荡器的分频器的驱动脉冲响应的计时器的步进速度的加速或减速，从OR门获取一系列这样的驱动脉冲，其中输入接收基本脉冲串 phiγ是与脉冲串phiγ间隔地交错的正常存在的第一辅助脉冲串phiβ和具有与其他两个脉冲序列的脉冲位置偏移的脉冲位置的正常缺少的第二辅助脉冲串phiα。 为了延迟时计，火车phi beta的脉冲被阻挡一段期望的时间; 为了使其前进，列车速率α的脉冲以取决于从分频器的低频级输出的组合选择合成的一系列控制脉冲的频率的速率内插。 外部选择信号被临时存储在包括具有与其反相输入端的正反馈连接的NOR门的存储器电路中，存储器电路通过以低于驱动脉冲的频率重复的复位脉冲周期性地测试。